diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index f70e47b..f2fb7bd 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -4190,8 +4190,8 @@ module mkCore(CLK, CASE_guard37769_0b0_sfdin45991_BITS_56_TO_34_0_ETC__q39, CASE_guard38131_0b0_theResult___snd46154_BITS__ETC__q110, CASE_guard38131_0b0_theResult___snd46154_BITS__ETC__q111, + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q40, CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41, - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q42, CASE_guard65896_0b0_sfdin73989_BITS_56_TO_34_0_ETC__q71, CASE_guard65896_0b0_sfdin73989_BITS_56_TO_34_0_ETC__q72, CASE_guard74603_0b0_theResult___snd82602_BITS__ETC__q69, @@ -4376,8 +4376,8 @@ module mkCore(CLK, CASE_guard11658_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q112, CASE_guard13789_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q189, CASE_guard13789_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q179, - CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q43, - CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q40, + CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q42, + CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q43, CASE_guard20365_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q115, CASE_guard20365_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q114, CASE_guard23101_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q185, @@ -4388,12 +4388,12 @@ module mkCore(CLK, CASE_guard29295_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q116, CASE_guard32170_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q187, CASE_guard32170_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q183, - CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q47, + CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48, CASE_guard37769_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q46, CASE_guard38131_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119, CASE_guard38131_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, CASE_guard46605_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, CASE_guard52990_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q156, CASE_guard52990_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q150, CASE_guard62302_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q154, @@ -6036,7 +6036,7 @@ module mkCore(CLK, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21514, NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21565, - NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708, + NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708, NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_deq_ETC___d25186, NOT_rob_deqPort_0_deq_data__3972_BITS_122_TO_1_ETC___d24474, NOT_rob_deqPort_0_deq_data__3972_BITS_122_TO_1_ETC___d24654, @@ -6545,8 +6545,8 @@ module mkCore(CLK, csrf_prv_reg_read__0001_ULE_1_4341_AND_IF_comm_ETC___d24381, csrf_prv_reg_read__0001_ULE_1___d24341, fetchStage_RDY_pipelines_0_first__9968_AND_NOT_ETC___d21158, + fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022, fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21220, - fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d21732, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d22237, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d22360, @@ -6601,7 +6601,7 @@ module mkCore(CLK, next_deqP___1__h403425, next_deqP___1__h406650, r__h699727, - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584, + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584, regRenamingTable_RDY_rename_1_getRename__1640__ETC___d21658, regRenamingTable_rename_0_canRename__1142_AND__ETC___d21215, regRenamingTable_rename_0_canRename__1142_AND__ETC___d21469, @@ -6742,7 +6742,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23120, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23187, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23472, - rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022, + rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712, specTagManager_canClaim__1140_AND_regRenamingT_ETC___d21875, specTagManager_canClaim__1140_AND_regRenamingT_ETC___d22170, v__h373723, @@ -6755,7 +6755,6 @@ module mkCore(CLK, v__h402945, v__h405939, v__h406170, - value_BIT_52___h521023, x__h684673; // action method coreReq_start @@ -9718,9 +9717,9 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && + l2Tlb$RDY_toChildren_rqFromC_put && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && - l2Tlb$RDY_toChildren_rqFromC_put ; + coreFix_memExe_dTlb$RDY_toParent_rqToP_first ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq @@ -9733,24 +9732,24 @@ module mkCore(CLK, // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = - coreFix_memExe_dTlb$RDY_toParent_flush_request_get && - l2Tlb$RDY_toChildren_dTlbReqFlush_put ; + l2Tlb$RDY_toChildren_dTlbReqFlush_put && + coreFix_memExe_dTlb$RDY_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; // rule RL_mkConnectionGetPut_1 @@ -9762,8 +9761,8 @@ module mkCore(CLK, // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - coreFix_memExe_dTlb$RDY_toParent_flush_response_put && l2Tlb$RDY_toChildren_flushDone_get && + coreFix_memExe_dTlb$RDY_toParent_flush_response_put && fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; @@ -10105,7 +10104,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_commitTrap[133] && @@ -10155,8 +10154,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[103] && rob$deqPort_0_deq_data[18] ; @@ -10236,7 +10235,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708 && + NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[103] && !rob$deqPort_0_deq_data[18] && @@ -10387,8 +10386,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10399,8 +10398,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10474,16 +10473,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -10494,8 +10493,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10533,8 +10532,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10631,8 +10630,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10649,8 +10648,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10672,8 +10671,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10820,8 +10819,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -10884,8 +10883,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11112,8 +11111,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11151,9 +11150,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + epochManager$RDY_incrementEpoch && fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty && epochManager$checkEpoch_0_check && fetchStage_pipelines_0_first__9971_BIT_4_0000__ETC___d20210 && @@ -11166,7 +11166,7 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022 && + fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d21037 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -22540,10 +22540,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__9971_BITS_98__ETC___d21597 = IF_fetchStage_pipelines_0_first__9971_BITS_98__ETC___d21590 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[98:96] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__9971_BIT_4_00_ETC___d21005 = @@ -22576,10 +22576,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d21677 && IF_fetchStage_RDY_pipelines_1_first__9979_AND__ETC___d21491 && (IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d21702 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712) ; + regRenamingTable$RDY_rename_1_claimRename && + rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712) ; assign IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d23959 = (fetchStage$pipelines_1_first[98:96] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__9969_9970_O_ETC___d22617 && @@ -24637,12 +24637,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_216_AND_rob_RDY_se_ETC___d1217 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_216_AND_rob_RDY_se_ETC___d1606 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -24714,10 +24714,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[4] || checkForException___d20207[4] || !rob$enqPort_0_canEnq ; - assign NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708 = + assign NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__4676_BIT_25_4677_4_ETC___d24705) ; @@ -24758,7 +24758,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[122:118] == 5'd15 || rob$deqPort_1_deq_data[122:118] == 5'd19 || rob$deqPort_1_deq_data[122:118] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21643 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21514 || @@ -31420,9 +31420,9 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__098_AND_coreFix_me_ETC___d24479 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__3972_BITS_122_TO_1_ETC___d24474 ; @@ -31495,6 +31495,14 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__9971_BITS_10_ETC___d21155 ; + assign fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022 = + fetchStage$RDY_pipelines_0_first && + fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[98:96] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21220 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[98:96] == 3'd1 && @@ -31502,12 +31510,6 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__9968_AND__ETC___d21162 ; - assign fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21708) && - (fetchStage$pipelines_1_first[98:96] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d21732 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__9971_BITS_98_ETC___d21729 && @@ -32342,7 +32344,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] % coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ; assign r__h699727 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584 = + assign regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_95_TO_9_ETC__q226 && (fetchStage$pipelines_0_first[103:99] == 5'd14 || @@ -33645,7 +33647,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h521023 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d10596, @@ -33657,7 +33660,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h521023 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d10607, @@ -33669,7 +33673,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h521023 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d10623, @@ -33681,7 +33686,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h521023 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d10636, @@ -33693,7 +33699,8 @@ module mkCore(CLK, 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && - (value_BIT_52___h521023 || + (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d10649 } ; @@ -33742,14 +33749,12 @@ module mkCore(CLK, guard__h662900 } ; assign result__h743379 = w__h743374 & y__h743408 ; assign result__h743430 = ~x__h743429 ; - assign rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[98:96] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21708) && + (fetchStage$pipelines_1_first[98:96] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__3972_BITS_186_TO_123_3_ETC___d24641 = rob$deqPort_0_deq_data[186:123] + 64'd4 ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q253 = @@ -33998,9 +34003,6 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 } ; - assign value_BIT_52___h521023 = - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != - 11'd0 ; assign value__h420742 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -34013,7 +34015,8 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; assign value__h512268 = { 1'b0, - value_BIT_52___h521023, + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != + 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; assign value__h563289 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; assign value__h563293 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; @@ -35041,23 +35044,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19:18]) - 2'd0: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = - coreFix_memExe_respLrScAmoQ_data_0[15:0]; - 2'd1: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = - coreFix_memExe_respLrScAmoQ_data_0[31:16]; - 2'd2: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = - coreFix_memExe_respLrScAmoQ_data_0[47:32]; - 2'd3: - SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = - coreFix_memExe_respLrScAmoQ_data_0[63:48]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -35086,6 +35072,23 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:56]; endcase end + always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19:18]) + 2'd0: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = + coreFix_memExe_respLrScAmoQ_data_0[15:0]; + 2'd1: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = + coreFix_memExe_respLrScAmoQ_data_0[31:16]; + 2'd2: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = + coreFix_memExe_respLrScAmoQ_data_0[47:32]; + 2'd3: + SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_154_ETC___d1559 = + coreFix_memExe_respLrScAmoQ_data_0[63:48]; + endcase + end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19]) @@ -35221,11 +35224,13 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5281 = - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d5331 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516] == + 2'd0; 1'd1: - SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5281 = - !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d5331 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516] == + 2'd0; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -35234,13 +35239,11 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d5331 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516] == - 2'd0; + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5281 = + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d5331 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516] == - 2'd0; + SEL_ARR_NOT_coreFix_memExe_dMem_cache_m_banks__ETC___d5281 = + !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or @@ -35633,57 +35636,19 @@ module mkCore(CLK, default: _theResult___fst_sfd__h446592 = 23'd0; endcase end - always@(guard__h420130 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h420130) - 2'b0, 2'b01, 2'b10: - CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q40 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q40 = - guard__h420130 == 2'b11 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q40 or - guard__h420130) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = - CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q40; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = - (guard__h420130 == 2'b0) ? - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h420130 == 2'b01 || guard__h420130 == 2'b10 || - guard__h420130 == 2'b11) && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == - 3'd4 && - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h446605 or _theResult___snd__h454628 or out_sfd__h455153 or _theResult___sfd__h455150) begin case (guard__h446605) 2'b0, 2'b01: - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41 = + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q40 = _theResult___snd__h454628[56:34]; 2'b10: - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41 = + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q40 = out_sfd__h455153; 2'b11: - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41 = + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q40 = _theResult___sfd__h455150; endcase end @@ -35692,16 +35657,16 @@ module mkCore(CLK, begin case (guard__h446605) 2'b0: - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q42 = + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41 = _theResult___snd__h454628[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q42 = + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41 = _theResult___sfd__h455150; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q40 or CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41 or - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q42 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7617 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7619 or _theResult___snd__h454628) @@ -35709,10 +35674,10 @@ module mkCore(CLK, case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: _theResult___fst_sfd__h455228 = - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41; + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q40; 3'd1: _theResult___fst_sfd__h455228 = - CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q42; + CASE_guard46605_0b0_theResult___snd54628_BITS__ETC__q41; 3'd2: _theResult___fst_sfd__h455228 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7617; @@ -35728,23 +35693,23 @@ module mkCore(CLK, begin case (guard__h420130) 2'b0, 2'b01, 2'b10: - CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q43 = + CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q42 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q43 = + CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q42 = guard__h420130 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q43 or + CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q42 or guard__h420130) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7649 = - CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q43; + CASE_guard20130_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q42; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7649 = (guard__h420130 == 2'b0) ? @@ -35761,6 +35726,44 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h420130 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h420130) + 2'b0, 2'b01, 2'b10: + CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q43 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q43 = + guard__h420130 == 2'b11 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q43 or + guard__h420130) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = + CASE_guard20130_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q43; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = + (guard__h420130 == 2'b0) ? + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + (guard__h420130 == 2'b01 || guard__h420130 == 2'b10 || + guard__h420130 == 2'b11) && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7705 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] == + 3'd4 && + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h428839 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -35875,66 +35878,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h437769 or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (guard__h437769) - 2'b0, 2'b01, 2'b10: - CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q47 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 2'd3: - CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q47 = - guard__h437769 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q47 or - guard__h437769) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = - CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q47; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = - (guard__h437769 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h437769 != 2'b01 && guard__h437769 != 2'b10 && - guard__h437769 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; - endcase - end always@(guard__h446605 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (guard__h446605) 2'b0, 2'b01, 2'b10: - CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = guard__h446605 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or guard__h446605) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7729 = - CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard46605_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7729 = (guard__h446605 == 2'b0) ? @@ -35951,6 +35916,44 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end + always@(guard__h437769 or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (guard__h437769) + 2'b0, 2'b01, 2'b10: + CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 2'd3: + CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 = + guard__h437769 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or + CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 or + guard__h437769) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = + CASE_guard37769_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = + (guard__h437769 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : + guard__h437769 != 2'b01 && guard__h437769 != 2'b10 && + guard__h437769 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d7679 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; + endcase + end always@(guard__h446605 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin @@ -39590,7 +39593,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__9971_BITS_95__ETC___d21237 or - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584 or + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1165_co_ETC___d21175 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__9971_BI_ETC___d21572 or @@ -39612,7 +39615,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[98:96] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__9971_BITS_95__ETC___d21237 || - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584; + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584; endcase end always@(fetchStage$pipelines_0_first or @@ -40052,28 +40055,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) - 3'd0, 3'd2, 3'd4: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - 3'd1: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985; - 3'd3: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802 or @@ -40140,28 +40121,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or - IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2710) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) - 3'd0, 3'd2, 3'd4: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; - 3'd1: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = - IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766; - 3'd3: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2710 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; - default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912 or @@ -40206,6 +40165,50 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) + 3'd0, 3'd2, 3'd4: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + 3'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985; + 3'd3: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or + IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2710) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) + 3'd0, 3'd2, 3'd4: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; + 3'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = + IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766; + 3'd3: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2710 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3964 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v index 6d2ef3b..1727e7e 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v @@ -7,6 +7,7 @@ // Ports: // Name I/O size props // RDY_set_verbosity O 1 const +// RDY_set_htif_addrs O 1 const // RDY_cpu_reset_server_request_put O 1 reg // RDY_cpu_reset_server_response_get O 1 reg // cpu_imem_master_awvalid O 1 @@ -71,6 +72,8 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 reg // set_verbosity_logdelay I 64 unused +// set_htif_addrs_tohost_addr I 64 reg +// set_htif_addrs_fromhost_addr I 64 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 @@ -111,6 +114,7 @@ // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 // debug_external_interrupt_req_set_not_clear I 1 // EN_set_verbosity I 1 +// EN_set_htif_addrs I 1 // EN_cpu_reset_server_request_put I 1 // EN_cpu_reset_server_response_get I 1 // @@ -140,6 +144,11 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, + set_htif_addrs_tohost_addr, + set_htif_addrs_fromhost_addr, + EN_set_htif_addrs, + RDY_set_htif_addrs, + EN_cpu_reset_server_request_put, RDY_cpu_reset_server_request_put, @@ -336,6 +345,12 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; + // action method set_htif_addrs + input [63 : 0] set_htif_addrs_tohost_addr; + input [63 : 0] set_htif_addrs_fromhost_addr; + input EN_set_htif_addrs; + output RDY_set_htif_addrs; + // action method cpu_reset_server_request_put input EN_cpu_reset_server_request_put; output RDY_cpu_reset_server_request_put; @@ -668,6 +683,7 @@ module mkCoreW(CLK, cpu_imem_master_awburst; wire RDY_cpu_reset_server_request_put, RDY_cpu_reset_server_response_get, + RDY_set_htif_addrs, RDY_set_verbosity, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, @@ -686,6 +702,16 @@ module mkCoreW(CLK, cpu_imem_master_wlast, cpu_imem_master_wvalid; + // register rg_fromhost_addr + reg [63 : 0] rg_fromhost_addr; + wire [63 : 0] rg_fromhost_addr$D_IN; + wire rg_fromhost_addr$EN; + + // register rg_tohost_addr + reg [63 : 0] rg_tohost_addr; + wire [63 : 0] rg_tohost_addr$D_IN; + wire rg_tohost_addr$EN; + // ports of submodule f_reset_reqs wire f_reset_reqs$CLR, f_reset_reqs$DEQ, @@ -1094,6 +1120,7 @@ module mkCoreW(CLK, CAN_FIRE_cpu_reset_server_request_put, CAN_FIRE_cpu_reset_server_response_get, CAN_FIRE_debug_external_interrupt_req, + CAN_FIRE_set_htif_addrs, CAN_FIRE_set_verbosity, WILL_FIRE_RL_rl_cpu_hart0_reset_complete, WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, @@ -1148,14 +1175,15 @@ module mkCoreW(CLK, WILL_FIRE_cpu_reset_server_request_put, WILL_FIRE_cpu_reset_server_response_get, WILL_FIRE_debug_external_interrupt_req, + WILL_FIRE_set_htif_addrs, WILL_FIRE_set_verbosity; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h3853; - reg [31 : 0] v__h4065; - reg [31 : 0] v__h3847; - reg [31 : 0] v__h4059; + reg [31 : 0] v__h3921; + reg [31 : 0] v__h4134; + reg [31 : 0] v__h3915; + reg [31 : 0] v__h4128; // synopsys translate_on // action method set_verbosity @@ -1163,6 +1191,11 @@ module mkCoreW(CLK, assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; + // action method set_htif_addrs + assign RDY_set_htif_addrs = 1'd1 ; + assign CAN_FIRE_set_htif_addrs = 1'd1 ; + assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; + // action method cpu_reset_server_request_put assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; @@ -1994,6 +2027,14 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; + // register rg_fromhost_addr + assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; + assign rg_fromhost_addr$EN = EN_set_htif_addrs ; + + // register rg_tohost_addr + assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; + assign rg_tohost_addr$EN = EN_set_htif_addrs ; + // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; assign f_reset_reqs$DEQ = @@ -2228,9 +2269,9 @@ module mkCoreW(CLK, assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = 64'd0 ; + assign proc$start_fromhostAddr = rg_fromhost_addr ; assign proc$start_startpc = 64'h0000000000001000 ; - assign proc$start_tohostAddr = 64'h0000000080001000 ; + assign proc$start_tohostAddr = rg_tohost_addr ; assign proc$EN_hart0_server_reset_request_put = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign proc$EN_hart0_server_reset_response_get = @@ -2243,6 +2284,35 @@ module mkCoreW(CLK, assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + end + else + begin + if (rg_fromhost_addr$EN) + rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; + if (rg_tohost_addr$EN) + rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; + rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + // handling of system tasks // synopsys translate_off @@ -2252,24 +2322,24 @@ module mkCoreW(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin - v__h3853 = $stime; + v__h3921 = $stime; #0; end - v__h3847 = v__h3853 / 32'd10; + v__h3915 = v__h3921 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h3847); + $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h3915); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) begin - v__h4065 = $stime; + v__h4134 = $stime; #0; end - v__h4059 = v__h4065 / 32'd10; + v__h4128 = v__h4134 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h4059); + v__h4128); end // synopsys translate_on endmodule // mkCoreW diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v index 798b647..fd7b6b8 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v @@ -2672,7 +2672,7 @@ module mkFetchStage(CLK, x__h153392, x__h153412; reg [31 : 0] CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q169, - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200, + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q180, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, IF_SEL_ARR_NOT_instdata_data_0_982_BIT_32_983__ETC___d4048, @@ -2682,9 +2682,9 @@ module mkFetchStage(CLK, reg [11 : 0] CASE_decode_049_BITS_72_TO_61_1_decode_049_BIT_ETC__q7, CASE_decode_891_BITS_72_TO_61_1_decode_891_BIT_ETC__q4, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q192, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196; + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197; reg [9 : 0] CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q193, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197; + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198; reg [4 : 0] CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q14, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q166, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q182, @@ -2788,16 +2788,16 @@ module mkFetchStage(CLK, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q120, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q121, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q122, + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q159, + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q160, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q161, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q163, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q165, - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q194, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q195, - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q24, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q27, @@ -2873,7 +2873,6 @@ module mkFetchStage(CLK, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q147, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q148, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q149, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q150, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q151, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q152, @@ -2883,15 +2882,16 @@ module mkFetchStage(CLK, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q156, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q157, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q158, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q170, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q171, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q174, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q176, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198, + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199, + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25, @@ -12490,9 +12490,9 @@ module mkFetchStage(CLK, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q194, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q195 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d7623 = - { CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 } ; + { CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15, + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d7632 = { SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d7623, CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, @@ -12523,7 +12523,7 @@ module mkFetchStage(CLK, IF_SEL_ARR_out_fifo_internalFifos_0_first__535_ETC___d7732, NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d7935 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d8141 = - { CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200, + { CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d7936, NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d8140 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d8142 = @@ -12531,14 +12531,14 @@ module mkFetchStage(CLK, SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d7566, SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d8141 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d8151 = - { CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197, + { CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199 } ; + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199, + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d8167 = - { CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 } ; + { CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d8170 = { SEL_ARR_out_fifo_internalFifos_0_first__535_BI_ETC___d8167, CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, @@ -13004,20 +13004,20 @@ module mkFetchStage(CLK, f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin case (f22f3_deqP) - 2'd0: x__h121037 = f22f3_data_0[138:75]; - 2'd1: x__h121037 = f22f3_data_1[138:75]; - 2'd2: x__h121037 = f22f3_data_2[138:75]; - 2'd3: x__h121037 = f22f3_data_3[138:75]; + 2'd0: x__h121030 = f22f3_data_0[203]; + 2'd1: x__h121030 = f22f3_data_1[203]; + 2'd2: x__h121030 = f22f3_data_2[203]; + 2'd3: x__h121030 = f22f3_data_3[203]; endcase end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin case (f22f3_deqP) - 2'd0: x__h121030 = f22f3_data_0[203]; - 2'd1: x__h121030 = f22f3_data_1[203]; - 2'd2: x__h121030 = f22f3_data_2[203]; - 2'd3: x__h121030 = f22f3_data_3[203]; + 2'd0: x__h121037 = f22f3_data_0[138:75]; + 2'd1: x__h121037 = f22f3_data_1[138:75]; + 2'd2: x__h121037 = f22f3_data_2[138:75]; + 2'd3: x__h121037 = f22f3_data_3[138:75]; endcase end always@(f22f3_deqP or @@ -15212,22 +15212,6 @@ module mkFetchStage(CLK, 4'd13; endcase end - always@(f22f3_data_1) - begin - case (f22f3_data_1[9:6]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = - f22f3_data_1[9:6]; - 4'd11: - IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = 4'd10; - 4'd12: - IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = 4'd11; - 4'd13: - IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = 4'd12; - default: IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = - 4'd13; - endcase - end always@(f22f3_data_2) begin case (f22f3_data_2[9:6]) @@ -15244,6 +15228,22 @@ module mkFetchStage(CLK, 4'd13; endcase end + always@(f22f3_data_1) + begin + case (f22f3_data_1[9:6]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = + f22f3_data_1[9:6]; + 4'd11: + IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = 4'd10; + 4'd12: + IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = 4'd11; + 4'd13: + IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = 4'd12; + default: IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 = + 4'd13; + endcase + end always@(f22f3_data_3) begin case (f22f3_data_3[9:6]) @@ -15385,31 +15385,6 @@ module mkFetchStage(CLK, 4'd8; endcase end - always@(f22f3_deqP or - IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 or - IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 or - IF_f22f3_data_2_651_BITS_9_TO_6_808_EQ_0_809_O_ETC___d3834 or - IF_f22f3_data_3_654_BITS_9_TO_6_836_EQ_0_837_O_ETC___d3862) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = - IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 == - 4'd6; - 2'd1: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = - IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 == - 4'd6; - 2'd2: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = - IF_f22f3_data_2_651_BITS_9_TO_6_808_EQ_0_809_O_ETC___d3834 == - 4'd6; - 2'd3: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = - IF_f22f3_data_3_654_BITS_9_TO_6_836_EQ_0_837_O_ETC___d3862 == - 4'd6; - endcase - end always@(f22f3_deqP or IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 or IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 or @@ -15443,21 +15418,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 == - 4'd5; + 4'd6; 2'd1: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 == - 4'd5; + 4'd6; 2'd2: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = IF_f22f3_data_2_651_BITS_9_TO_6_808_EQ_0_809_O_ETC___d3834 == - 4'd5; + 4'd6; 2'd3: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3901 = IF_f22f3_data_3_654_BITS_9_TO_6_836_EQ_0_837_O_ETC___d3862 == - 4'd5; + 4'd6; endcase end always@(f22f3_deqP or @@ -15493,21 +15468,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 == - 4'd2; + 4'd5; 2'd1: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 == - 4'd2; + 4'd5; 2'd2: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = IF_f22f3_data_2_651_BITS_9_TO_6_808_EQ_0_809_O_ETC___d3834 == - 4'd2; + 4'd5; 2'd3: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3895 = IF_f22f3_data_3_654_BITS_9_TO_6_836_EQ_0_837_O_ETC___d3862 == - 4'd2; + 4'd5; endcase end always@(f22f3_deqP or @@ -15543,21 +15518,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 == - 4'd1; + 4'd2; 2'd1: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 == - 4'd1; + 4'd2; 2'd2: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = IF_f22f3_data_2_651_BITS_9_TO_6_808_EQ_0_809_O_ETC___d3834 == - 4'd1; + 4'd2; 2'd3: - SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3877 = IF_f22f3_data_3_654_BITS_9_TO_6_836_EQ_0_837_O_ETC___d3862 == - 4'd1; + 4'd2; endcase end always@(f22f3_deqP or @@ -15585,15 +15560,29 @@ module mkFetchStage(CLK, 4'd0; endcase end - always@(f32d_deqP or f32d_data_0 or f32d_data_1) + always@(f22f3_deqP or + IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 or + IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 or + IF_f22f3_data_2_651_BITS_9_TO_6_808_EQ_0_809_O_ETC___d3834 or + IF_f22f3_data_3_654_BITS_9_TO_6_836_EQ_0_837_O_ETC___d3862) begin - case (f32d_deqP) - 1'd0: - SEL_ARR_f32d_data_0_974_BITS_3_TO_0_975_f32d_d_ETC___d3979 = - f32d_data_0[3:0]; - 1'd1: - SEL_ARR_f32d_data_0_974_BITS_3_TO_0_975_f32d_d_ETC___d3979 = - f32d_data_1[3:0]; + case (f22f3_deqP) + 2'd0: + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_0_753_O_ETC___d3778 == + 4'd1; + 2'd1: + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + IF_f22f3_data_1_648_BITS_9_TO_6_780_EQ_0_781_O_ETC___d3806 == + 4'd1; + 2'd2: + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + IF_f22f3_data_2_651_BITS_9_TO_6_808_EQ_0_809_O_ETC___d3834 == + 4'd1; + 2'd3: + SEL_ARR_IF_f22f3_data_0_645_BITS_9_TO_6_752_EQ_ETC___d3871 = + IF_f22f3_data_3_654_BITS_9_TO_6_836_EQ_0_837_O_ETC___d3862 == + 4'd1; endcase end always@(f22f3_deqP or @@ -15614,6 +15603,17 @@ module mkFetchStage(CLK, f22f3_data_3[202:139]; endcase end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + SEL_ARR_f32d_data_0_974_BITS_3_TO_0_975_f32d_d_ETC___d3979 = + f32d_data_0[3:0]; + 1'd1: + SEL_ARR_f32d_data_0_974_BITS_3_TO_0_975_f32d_d_ETC___d3979 = + f32d_data_1[3:0]; + endcase + end always@(n__read__h122744 or instdata_data_0 or instdata_data_1) begin case (n__read__h122744) @@ -16235,75 +16235,75 @@ module mkFetchStage(CLK, 4'd13; endcase end - always@(x__h72923 or + always@(x__h62899 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72923) + case (x__h62899) 1'd0: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15 = + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15 = out_fifo_internalFifos_0$D_OUT[87]; 1'd1: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15 = + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q15 = out_fifo_internalFifos_1$D_OUT[87]; endcase end - always@(x__h72923 or + always@(x__h62899 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72923) + case (x__h62899) 1'd0: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16 = + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16 = out_fifo_internalFifos_0$D_OUT[86]; 1'd1: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16 = + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16 = out_fifo_internalFifos_1$D_OUT[86]; endcase end - always@(x__h72923 or + always@(x__h62899 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72923) + case (x__h62899) 1'd0: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = out_fifo_internalFifos_0$D_OUT[85]; 1'd1: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = out_fifo_internalFifos_1$D_OUT[85]; endcase end - always@(x__h62899 or + always@(x__h72923 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62899) + case (x__h72923) 1'd0: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = out_fifo_internalFifos_0$D_OUT[87]; 1'd1: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = out_fifo_internalFifos_1$D_OUT[87]; endcase end - always@(x__h62899 or + always@(x__h72923 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62899) + case (x__h72923) 1'd0: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = out_fifo_internalFifos_0$D_OUT[86]; 1'd1: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = out_fifo_internalFifos_1$D_OUT[86]; endcase end - always@(x__h62899 or + always@(x__h72923 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62899) + case (x__h72923) 1'd0: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = out_fifo_internalFifos_0$D_OUT[85]; 1'd1: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = out_fifo_internalFifos_1$D_OUT[85]; endcase end @@ -16574,6 +16574,21 @@ module mkFetchStage(CLK, out_fifo_internalFifos_1$D_OUT[86:82]; endcase end + always@(IF_NOT_IF_pc_reg_dummy2_0_read__341_AND_pc_reg_ETC___d3371 or + IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3355 or + IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3364) + begin + case (IF_NOT_IF_pc_reg_dummy2_0_read__341_AND_pc_reg_ETC___d3371) + 32'd0: + pred_next_pc__h114511 = + IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3355; + 32'd1: + pred_next_pc__h114511 = + IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3364; + default: pred_next_pc__h114511 = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin @@ -16592,21 +16607,6 @@ module mkFetchStage(CLK, f22f3_data_3[3:0]; endcase end - always@(IF_NOT_IF_pc_reg_dummy2_0_read__341_AND_pc_reg_ETC___d3371 or - IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3355 or - IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3364) - begin - case (IF_NOT_IF_pc_reg_dummy2_0_read__341_AND_pc_reg_ETC___d3371) - 32'd0: - pred_next_pc__h114511 = - IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3355; - 32'd1: - pred_next_pc__h114511 = - IF_SEL_ARR_nextAddrPred_valid_0_read__084_next_ETC___d3364; - default: pred_next_pc__h114511 = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin @@ -18586,15 +18586,27 @@ module mkFetchStage(CLK, out_fifo_internalFifos_1$D_OUT[136]; endcase end + always@(x__h62899 or + out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) + begin + case (x__h62899) + 1'd0: + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196 = + out_fifo_internalFifos_0$D_OUT[135:104]; + 1'd1: + CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196 = + out_fifo_internalFifos_1$D_OUT[135:104]; + endcase + end always@(x__h72923 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin case (x__h72923) 1'd0: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197 = out_fifo_internalFifos_0$D_OUT[159:148]; 1'd1: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197 = out_fifo_internalFifos_1$D_OUT[159:148]; endcase end @@ -18603,10 +18615,10 @@ module mkFetchStage(CLK, begin case (x__h72923) 1'd0: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198 = out_fifo_internalFifos_0$D_OUT[147:138]; 1'd1: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198 = out_fifo_internalFifos_1$D_OUT[147:138]; endcase end @@ -18615,10 +18627,10 @@ module mkFetchStage(CLK, begin case (x__h72923) 1'd0: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199 = out_fifo_internalFifos_0$D_OUT[137]; 1'd1: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q198 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199 = out_fifo_internalFifos_1$D_OUT[137]; endcase end @@ -18627,25 +18639,13 @@ module mkFetchStage(CLK, begin case (x__h72923) 1'd0: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200 = out_fifo_internalFifos_0$D_OUT[136]; 1'd1: - CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q199 = + CASE_x2923_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200 = out_fifo_internalFifos_1$D_OUT[136]; endcase end - always@(x__h62899 or - out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) - begin - case (x__h62899) - 1'd0: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200 = - out_fifo_internalFifos_0$D_OUT[135:104]; - 1'd1: - CASE_x2899_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q200 = - out_fifo_internalFifos_1$D_OUT[135:104]; - endcase - end always@(x__h72923 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v index 7fe1e72..70097b3 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v @@ -1719,7 +1719,7 @@ module mkLLCache(CLK, CASE_cache_cRqMshrstuck_get_BITS_3_TO_2_0_cac_ETC__q2, CASE_cache_cRqMshrstuck_get_BITS_7_TO_6_0_cac_ETC__q1, CASE_cache_pipelinefirst_BIT_577_0_cache_cRqM_ETC__q13, - CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q150, + CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q148, CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q179, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q159, CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q165, @@ -1730,7 +1730,7 @@ module mkLLCache(CLK, reg CASE_cache_pipelinefirst_BIT_577_0_NOT_cache__ETC__q15, CASE_cache_pipelinefirst_BIT_577_0_cache_cRqM_ETC__q14, CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6, - CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q151, + CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q149, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q10, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q100, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q101, @@ -1756,8 +1756,8 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q137, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q140, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q141, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q148, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q149, + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150, + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q28, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q29, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q32, @@ -4893,15 +4893,7 @@ module mkLLCache(CLK, assign cache_rsLdToDmaQ_clearReq_rl$EN = 1'd1 ; // register cache_rsLdToDmaQ_data_0 - assign cache_rsLdToDmaQ_data_0$D_IN = cache_rsLdToDmaQ_data_1$D_IN ; - assign cache_rsLdToDmaQ_data_0$EN = - cache_rsLdToDmaQ_enqP == 1'd0 && - NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && - cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT && - IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__70_THEN_ETC___d579 ; - - // register cache_rsLdToDmaQ_data_1 - assign cache_rsLdToDmaQ_data_1$D_IN = + assign cache_rsLdToDmaQ_data_0$D_IN = { CAN_FIRE_RL_cache_sendRsLdToDma ? cache_rsLdToDmaQ_enqReq_lat_0$wget[516:5] : cache_rsLdToDmaQ_enqReq_rl[516:5], @@ -4913,6 +4905,14 @@ module mkLLCache(CLK, CAN_FIRE_RL_cache_sendRsLdToDma ? cache_rsLdToDmaQ_enqReq_lat_0$wget[3:0] : cache_rsLdToDmaQ_enqReq_rl[3:0] } ; + assign cache_rsLdToDmaQ_data_0$EN = + cache_rsLdToDmaQ_enqP == 1'd0 && + NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && + cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT && + IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__70_THEN_ETC___d579 ; + + // register cache_rsLdToDmaQ_data_1 + assign cache_rsLdToDmaQ_data_1$D_IN = cache_rsLdToDmaQ_data_0$D_IN ; assign cache_rsLdToDmaQ_data_1$EN = cache_rsLdToDmaQ_enqP == 1'd1 && NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && @@ -5258,7 +5258,13 @@ module mkLLCache(CLK, assign cache_toMQ_clearReq_rl$EN = 1'd1 ; // register cache_toMQ_data_0 - assign cache_toMQ_data_0$D_IN = cache_toMQ_data_1$D_IN ; + assign cache_toMQ_data_0$D_IN = + { !cache_toMQ_enqReq_dummy2_2$Q_OUT || + IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_NOT_c_ETC___d828 || + (cache_toMQ_enqReq_lat_0$whas ? + cache_toMQ_enqReq_lat_0$wget[640] : + cache_toMQ_enqReq_rl[640]), + IF_cache_toMQ_enqReq_dummy2_2_read__86_AND_IF__ETC___d931 } ; assign cache_toMQ_data_0$EN = cache_toMQ_enqP == 1'd0 && NOT_cache_toMQ_clearReq_dummy2_1_read__80_81_O_ETC___d885 && @@ -5266,13 +5272,7 @@ module mkLLCache(CLK, IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_cache_ETC___d821 ; // register cache_toMQ_data_1 - assign cache_toMQ_data_1$D_IN = - { !cache_toMQ_enqReq_dummy2_2$Q_OUT || - IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_NOT_c_ETC___d828 || - (cache_toMQ_enqReq_lat_0$whas ? - cache_toMQ_enqReq_lat_0$wget[640] : - cache_toMQ_enqReq_rl[640]), - IF_cache_toMQ_enqReq_dummy2_2_read__86_AND_IF__ETC___d931 } ; + assign cache_toMQ_data_1$D_IN = cache_toMQ_data_0$D_IN ; assign cache_toMQ_data_1$EN = cache_toMQ_enqP == 1'd1 && NOT_cache_toMQ_clearReq_dummy2_1_read__80_81_O_ETC___d885 && @@ -11066,8 +11066,8 @@ module mkLLCache(CLK, CASE_cache_pipelinefirst_BIT_577_0_cache_cRqM_ETC__q13 < SEL_ARR_cache_pipeline_first__265_BITS_519_TO__ETC___d7812 ; assign SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1514 = - { CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q150, - CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q151, + { CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q148, + CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q149, x__h237769, 67'h55555555555555552, x__h244358 } ; @@ -11194,8 +11194,8 @@ module mkLLCache(CLK, CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q141 } ; assign SEL_ARR_cache_rqFromDmaQ_data_0_571_BIT_580_01_ETC___d2248 = { SEL_ARR_cache_rqFromDmaQ_data_0_571_BIT_580_01_ETC___d2243, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q148, - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q149 } ; + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150, + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151 } ; assign SEL_ARR_cache_rsFromCQ_data_0_376_BITS_579_TO__ETC___d2435 = { SEL_ARR_cache_rsFromCQ_data_0_376_BITS_579_TO__ETC___d2381, CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q159, @@ -12066,15 +12066,15 @@ module mkLLCache(CLK, always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) - 1'd0: x__h530413 = cache_toCQ_data_0[516]; - 1'd1: x__h530413 = cache_toCQ_data_1[516]; + 1'd0: x__h530368 = cache_toCQ_data_0[0]; + 1'd1: x__h530368 = cache_toCQ_data_1[0]; endcase end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) - 1'd0: x__h530368 = cache_toCQ_data_0[0]; - 1'd1: x__h530368 = cache_toCQ_data_1[0]; + 1'd0: x__h530413 = cache_toCQ_data_0[516]; + 1'd1: x__h530413 = cache_toCQ_data_1[516]; endcase end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) @@ -12103,16 +12103,16 @@ module mkLLCache(CLK, cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h282062 = cache_rsFromCQ_data_0[192:129]; - 1'd1: value__h282062 = cache_rsFromCQ_data_1[192:129]; + 1'd0: value__h281975 = cache_rsFromCQ_data_0[128:65]; + 1'd1: value__h281975 = cache_rsFromCQ_data_1[128:65]; endcase end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h281975 = cache_rsFromCQ_data_0[128:65]; - 1'd1: value__h281975 = cache_rsFromCQ_data_1[128:65]; + 1'd0: value__h282062 = cache_rsFromCQ_data_0[192:129]; + 1'd1: value__h282062 = cache_rsFromCQ_data_1[192:129]; endcase end always@(cache_rsFromCQ_deqP or @@ -12155,14 +12155,6 @@ module mkLLCache(CLK, 1'd1: value__h282497 = cache_rsFromCQ_data_1[512:449]; endcase end - always@(cache_rsFromMQ_deqP or - cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1) - begin - case (cache_rsFromMQ_deqP) - 1'd0: n__h282755 = cache_rsFromMQ_data_0[3:0]; - 1'd1: n__h282755 = cache_rsFromMQ_data_1[3:0]; - endcase - end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin @@ -12171,6 +12163,14 @@ module mkLLCache(CLK, 1'd1: x__h280952 = cache_rsFromCQ_data_1[0]; endcase end + always@(cache_rsFromMQ_deqP or + cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1) + begin + case (cache_rsFromMQ_deqP) + 1'd0: n__h282755 = cache_rsFromMQ_data_0[3:0]; + 1'd1: n__h282755 = cache_rsFromMQ_data_1[3:0]; + endcase + end always@(cache_rsToCIndexQ_deqP or cache_rsToCIndexQ_data_0 or cache_rsToCIndexQ_data_1 or @@ -12207,6 +12207,18 @@ module mkLLCache(CLK, 4'd15: n__h346646 = cache_rsToCIndexQ_data_15[5:2]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1687 = + !cache_rqFromDmaQ_data_0[532]; + 1'd1: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1687 = + !cache_rqFromDmaQ_data_1[532]; + endcase + end always@(cache_rqFromCQ_deqP or cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) begin @@ -12248,11 +12260,11 @@ module mkLLCache(CLK, begin case (cache_rqFromCQ_deqP) 1'd0: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1549 = - cache_rqFromCQ_data_0[6:5] == 2'd1; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1544 = + cache_rqFromCQ_data_0[6:5] == 2'd0; 1'd1: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1549 = - cache_rqFromCQ_data_1[6:5] == 2'd1; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1544 = + cache_rqFromCQ_data_1[6:5] == 2'd0; endcase end always@(cache_rqFromCQ_deqP or @@ -12260,11 +12272,11 @@ module mkLLCache(CLK, begin case (cache_rqFromCQ_deqP) 1'd0: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1544 = - cache_rqFromCQ_data_0[6:5] == 2'd0; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1549 = + cache_rqFromCQ_data_0[6:5] == 2'd1; 1'd1: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1544 = - cache_rqFromCQ_data_1[6:5] == 2'd0; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1549 = + cache_rqFromCQ_data_1[6:5] == 2'd1; endcase end always@(cache_rqFromCQ_deqP or @@ -12296,11 +12308,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1589 = - !cache_rqFromDmaQ_data_0[518]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1582 = + !cache_rqFromDmaQ_data_0[517]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1589 = - !cache_rqFromDmaQ_data_1[518]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1582 = + !cache_rqFromDmaQ_data_1[517]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12308,11 +12320,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1582 = - !cache_rqFromDmaQ_data_0[517]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1589 = + !cache_rqFromDmaQ_data_0[518]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1582 = - !cache_rqFromDmaQ_data_1[517]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_51_ETC___d1589 = + !cache_rqFromDmaQ_data_1[518]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12339,18 +12351,6 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[520]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = - !cache_rqFromDmaQ_data_0[522]; - 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = - !cache_rqFromDmaQ_data_1[522]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12368,11 +12368,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1624 = - !cache_rqFromDmaQ_data_0[523]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = + !cache_rqFromDmaQ_data_0[522]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1624 = - !cache_rqFromDmaQ_data_1[523]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = + !cache_rqFromDmaQ_data_1[522]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12387,6 +12387,18 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[524]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1624 = + !cache_rqFromDmaQ_data_0[523]; + 1'd1: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1624 = + !cache_rqFromDmaQ_data_1[523]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12416,11 +12428,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1659 = - !cache_rqFromDmaQ_data_0[528]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1652 = + !cache_rqFromDmaQ_data_0[527]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1659 = - !cache_rqFromDmaQ_data_1[528]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1652 = + !cache_rqFromDmaQ_data_1[527]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12428,11 +12440,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1652 = - !cache_rqFromDmaQ_data_0[527]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1659 = + !cache_rqFromDmaQ_data_0[528]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1652 = - !cache_rqFromDmaQ_data_1[527]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1659 = + !cache_rqFromDmaQ_data_1[528]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12483,18 +12495,6 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[533]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1687 = - !cache_rqFromDmaQ_data_0[532]; - 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1687 = - !cache_rqFromDmaQ_data_1[532]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12519,6 +12519,18 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[535]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1722 = + !cache_rqFromDmaQ_data_0[537]; + 1'd1: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1722 = + !cache_rqFromDmaQ_data_1[537]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12543,18 +12555,6 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[538]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1722 = - !cache_rqFromDmaQ_data_0[537]; - 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1722 = - !cache_rqFromDmaQ_data_1[537]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12584,11 +12584,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = - !cache_rqFromDmaQ_data_0[542]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1750 = + !cache_rqFromDmaQ_data_0[541]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = - !cache_rqFromDmaQ_data_1[542]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1750 = + !cache_rqFromDmaQ_data_1[541]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12596,11 +12596,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1750 = - !cache_rqFromDmaQ_data_0[541]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = + !cache_rqFromDmaQ_data_0[542]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1750 = - !cache_rqFromDmaQ_data_1[541]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = + !cache_rqFromDmaQ_data_1[542]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12620,11 +12620,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1771 = - !cache_rqFromDmaQ_data_0[544]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = + !cache_rqFromDmaQ_data_0[545]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1771 = - !cache_rqFromDmaQ_data_1[544]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = + !cache_rqFromDmaQ_data_1[545]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12632,11 +12632,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = - !cache_rqFromDmaQ_data_0[545]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1771 = + !cache_rqFromDmaQ_data_0[544]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = - !cache_rqFromDmaQ_data_1[545]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1771 = + !cache_rqFromDmaQ_data_1[544]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12656,11 +12656,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1799 = - !cache_rqFromDmaQ_data_0[548]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1792 = + !cache_rqFromDmaQ_data_0[547]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1799 = - !cache_rqFromDmaQ_data_1[548]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1792 = + !cache_rqFromDmaQ_data_1[547]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12668,11 +12668,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1792 = - !cache_rqFromDmaQ_data_0[547]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1799 = + !cache_rqFromDmaQ_data_0[548]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1792 = - !cache_rqFromDmaQ_data_1[547]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1799 = + !cache_rqFromDmaQ_data_1[548]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12704,11 +12704,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1827 = - !cache_rqFromDmaQ_data_0[552]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1820 = + !cache_rqFromDmaQ_data_0[551]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1827 = - !cache_rqFromDmaQ_data_1[552]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1820 = + !cache_rqFromDmaQ_data_1[551]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12716,11 +12716,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1820 = - !cache_rqFromDmaQ_data_0[551]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1827 = + !cache_rqFromDmaQ_data_0[552]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1820 = - !cache_rqFromDmaQ_data_1[551]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1827 = + !cache_rqFromDmaQ_data_1[552]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12740,11 +12740,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1848 = - !cache_rqFromDmaQ_data_0[555]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1841 = + !cache_rqFromDmaQ_data_0[554]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1848 = - !cache_rqFromDmaQ_data_1[555]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1841 = + !cache_rqFromDmaQ_data_1[554]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12752,11 +12752,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1841 = - !cache_rqFromDmaQ_data_0[554]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1848 = + !cache_rqFromDmaQ_data_0[555]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1841 = - !cache_rqFromDmaQ_data_1[554]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1848 = + !cache_rqFromDmaQ_data_1[555]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12788,11 +12788,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1876 = - !cache_rqFromDmaQ_data_0[559]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1869 = + !cache_rqFromDmaQ_data_0[558]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1876 = - !cache_rqFromDmaQ_data_1[559]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1869 = + !cache_rqFromDmaQ_data_1[558]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12800,11 +12800,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1869 = - !cache_rqFromDmaQ_data_0[558]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1876 = + !cache_rqFromDmaQ_data_0[559]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1869 = - !cache_rqFromDmaQ_data_1[558]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1876 = + !cache_rqFromDmaQ_data_1[559]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12860,11 +12860,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1911 = - !cache_rqFromDmaQ_data_0[564]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1918 = + !cache_rqFromDmaQ_data_0[565]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1911 = - !cache_rqFromDmaQ_data_1[564]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1918 = + !cache_rqFromDmaQ_data_1[565]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12872,11 +12872,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1918 = - !cache_rqFromDmaQ_data_0[565]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1911 = + !cache_rqFromDmaQ_data_0[564]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1918 = - !cache_rqFromDmaQ_data_1[565]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1911 = + !cache_rqFromDmaQ_data_1[564]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13088,11 +13088,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_516_T_ETC___d2336 = - cache_rqFromDmaQ_data_0[516:453]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_452_T_ETC___d2340 = + cache_rqFromDmaQ_data_0[452:389]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_516_T_ETC___d2336 = - cache_rqFromDmaQ_data_1[516:453]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_452_T_ETC___d2340 = + cache_rqFromDmaQ_data_1[452:389]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13100,11 +13100,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_452_T_ETC___d2340 = - cache_rqFromDmaQ_data_0[452:389]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_516_T_ETC___d2336 = + cache_rqFromDmaQ_data_0[516:453]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_452_T_ETC___d2340 = - cache_rqFromDmaQ_data_1[452:389]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_516_T_ETC___d2336 = + cache_rqFromDmaQ_data_1[516:453]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13136,11 +13136,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_196_T_ETC___d2358 = - cache_rqFromDmaQ_data_0[196:133]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_260_T_ETC___d2354 = + cache_rqFromDmaQ_data_0[260:197]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_196_T_ETC___d2358 = - cache_rqFromDmaQ_data_1[196:133]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_260_T_ETC___d2354 = + cache_rqFromDmaQ_data_1[260:197]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13148,11 +13148,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_260_T_ETC___d2354 = - cache_rqFromDmaQ_data_0[260:197]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_196_T_ETC___d2358 = + cache_rqFromDmaQ_data_0[196:133]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_260_T_ETC___d2354 = - cache_rqFromDmaQ_data_1[260:197]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_196_T_ETC___d2358 = + cache_rqFromDmaQ_data_1[196:133]; endcase end always@(cache_rsFromCQ_deqP or @@ -13244,11 +13244,11 @@ module mkLLCache(CLK, begin case (cache_rsFromMQ_deqP) 1'd0: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_324_TO__ETC___d2493 = - cache_rsFromMQ_data_0[324:261]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_260_TO__ETC___d2498 = + cache_rsFromMQ_data_0[260:197]; 1'd1: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_324_TO__ETC___d2493 = - cache_rsFromMQ_data_1[324:261]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_260_TO__ETC___d2498 = + cache_rsFromMQ_data_1[260:197]; endcase end always@(cache_rsFromMQ_deqP or @@ -13256,11 +13256,11 @@ module mkLLCache(CLK, begin case (cache_rsFromMQ_deqP) 1'd0: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_260_TO__ETC___d2498 = - cache_rsFromMQ_data_0[260:197]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_324_TO__ETC___d2493 = + cache_rsFromMQ_data_0[324:261]; 1'd1: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_260_TO__ETC___d2498 = - cache_rsFromMQ_data_1[260:197]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_324_TO__ETC___d2493 = + cache_rsFromMQ_data_1[324:261]; endcase end always@(cache_rsFromMQ_deqP or @@ -13423,25 +13423,6 @@ module mkLLCache(CLK, cache_rsToCIndexQ_data_15[1:0] == 2'd1; endcase end - always@(cache_pipeline$unguard_first or - cache_cRqMshr$sendRqToC_searchNeedRqChild) - begin - case (cache_pipeline$unguard_first[582:581]) - 2'd0: - CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - cache_pipeline$unguard_first[580:577] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - 2'd1: - CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - !cache_pipeline$unguard_first[517] || - cache_pipeline$unguard_first[516:513] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - default: CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - !cache_pipeline$unguard_first[517] || - cache_pipeline$unguard_first[516:513] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - endcase - end always@(cache_rsToCIndexQ_deqP or cache_rsToCIndexQ_data_0 or cache_rsToCIndexQ_data_1 or @@ -13510,6 +13491,25 @@ module mkLLCache(CLK, cache_rsToCIndexQ_data_15[1:0] == 2'd2; endcase end + always@(cache_pipeline$unguard_first or + cache_cRqMshr$sendRqToC_searchNeedRqChild) + begin + case (cache_pipeline$unguard_first[582:581]) + 2'd0: + CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + cache_pipeline$unguard_first[580:577] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + 2'd1: + CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + !cache_pipeline$unguard_first[517] || + cache_pipeline$unguard_first[516:513] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + default: CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + !cache_pipeline$unguard_first[517] || + cache_pipeline$unguard_first[516:513] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + endcase + end always@(child__h356786 or cache_cRqMshr$sendRqToC_getSlot) begin case (child__h356786) @@ -13760,6 +13760,17 @@ module mkLLCache(CLK, cache_toCQ_data_1[194:131]; endcase end + always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) + begin + case (cache_toMQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_toMQ_data_0_881_BIT_640_882__ETC___d9888 = + !cache_toMQ_data_0[640]; + 1'd1: + SEL_ARR_NOT_cache_toMQ_data_0_881_BIT_640_882__ETC___d9888 = + !cache_toMQ_data_1[640]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -13773,17 +13784,6 @@ module mkLLCache(CLK, endcase end always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) - begin - case (cache_toMQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_toMQ_data_0_881_BIT_640_882__ETC___d9888 = - !cache_toMQ_data_0[640]; - 1'd1: - SEL_ARR_NOT_cache_toMQ_data_0_881_BIT_640_882__ETC___d9888 = - !cache_toMQ_data_1[640]; - endcase - end - always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1) begin case (cache_toMQ_deqP) 1'd0: @@ -15274,39 +15274,15 @@ module mkLLCache(CLK, cache_rqFromDmaQ_data_1[132:69]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q148 = - cache_rqFromDmaQ_data_0[518]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q148 = - cache_rqFromDmaQ_data_1[518]; - endcase - end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q149 = - cache_rqFromDmaQ_data_0[517]; - 1'd1: - CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q149 = - cache_rqFromDmaQ_data_1[517]; - endcase - end always@(cache_rqFromCQ_deqP or cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1) begin case (cache_rqFromCQ_deqP) 1'd0: - CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q150 = + CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q148 = cache_rqFromCQ_data_0[6:5]; 1'd1: - CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q150 = + CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q148 = cache_rqFromCQ_data_1[6:5]; endcase end @@ -15315,13 +15291,37 @@ module mkLLCache(CLK, begin case (cache_rqFromCQ_deqP) 1'd0: - CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q151 = + CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q149 = cache_rqFromCQ_data_0[4]; 1'd1: - CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q151 = + CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q149 = cache_rqFromCQ_data_1[4]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150 = + cache_rqFromDmaQ_data_0[518]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150 = + cache_rqFromDmaQ_data_1[518]; + endcase + end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151 = + cache_rqFromDmaQ_data_0[517]; + 1'd1: + CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151 = + cache_rqFromDmaQ_data_1[517]; + endcase + end always@(cache_rsLdToDmaQ_deqP or cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1) begin diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v index 38cc003..b1fbb86 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v @@ -1370,7 +1370,7 @@ module mkLLPipeline(CLK, MUX_m_infoRam_4_bram$a_put_1__SEL_1, MUX_m_infoRam_5_bram$a_put_1__SEL_1, MUX_m_infoRam_6_bram$a_put_1__SEL_1, - MUX_m_infoRam_7_bram$a_put_2__SEL_1, + MUX_m_infoRam_7_bram$a_put_1__SEL_1, MUX_m_infoRam_8_bram$a_put_1__SEL_1, MUX_m_infoRam_9_bram$a_put_1__SEL_1; @@ -1381,12 +1381,12 @@ module mkLLPipeline(CLK, // remaining internal signals reg [975 : 0] IF_send_r_BITS_583_TO_582_921_EQ_0_922_THEN_m__ETC___d4178; - reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3; + reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21; reg [47 : 0] y_avValue_info_tag__h200377; reg [3 : 0] CASE_send_r_BITS_583_TO_582_0_send_r_BITS_583__ETC__q2, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3892; - reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12, @@ -1398,7 +1398,7 @@ module mkLLPipeline(CLK, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20, - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21, + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8, @@ -4012,7 +4012,7 @@ module mkLLPipeline(CLK, EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd5 ; assign MUX_m_infoRam_6_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd6 ; - assign MUX_m_infoRam_7_bram$a_put_2__SEL_1 = + assign MUX_m_infoRam_7_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd7 ; assign MUX_m_infoRam_8_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd8 ; @@ -4022,11 +4022,11 @@ module mkLLPipeline(CLK, // inlined wires assign m_pipe_enq2Mat_lat_0$wget = { 1'd1, - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, IF_IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypa_ETC___d2113 } ; assign m_pipe_enq2Mat_lat_2$wget = { 1'd1, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21, IF_send_r_BITS_583_TO_582_921_EQ_0_922_THEN_m__ETC___d4199 } ; assign m_pipe_mat2Out_lat_0$wget = { deqWrite_swapRq[4], @@ -5220,12 +5220,12 @@ module mkLLPipeline(CLK, // submodule m_infoRam_7_bram assign m_infoRam_7_bram$ADDRA = - MUX_m_infoRam_7_bram$a_put_2__SEL_1 ? + MUX_m_infoRam_7_bram$a_put_1__SEL_1 ? addr__h287435[15:6] : m_initIndex ; assign m_infoRam_7_bram$ADDRB = m_infoRam_0_bram$ADDRB ; assign m_infoRam_7_bram$DIA = - MUX_m_infoRam_7_bram$a_put_2__SEL_1 ? + MUX_m_infoRam_7_bram$a_put_1__SEL_1 ? deqWrite_wrRam[571:512] : 60'd10 ; assign m_infoRam_7_bram$DIB = 60'hAAAAAAAAAAAAAAA /* unspecified value */ ; @@ -5995,7 +5995,7 @@ module mkLLPipeline(CLK, IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypass__ETC___d1611 || m_pipe_enq2Mat_rl[517], m_pipe_enq2Mat_rl[516:4], - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, m_pipe_enq2Mat_rl[1:0] } ; assign IF_IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m__ETC___d2634 = (IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 == @@ -10377,38 +10377,25 @@ module mkLLPipeline(CLK, { 2'd2, send_r[517:516] }; endcase end - always@(send_r) - begin - case (send_r[583:582]) - 2'd0: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd0, send_r[67:0] }; - 2'd1: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; - default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd2, send_r[581:518], send_r[3:0] }; - endcase - end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[3:2]) 2'd0, 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = m_pipe_enq2Mat_rl[3:2]; - default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = 2'd2; + default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = 2'd2; endcase end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[1563:1562]) 2'd0: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd0, m_pipe_enq2Mat_rl[1561:1494] }; 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = m_pipe_enq2Mat_rl[1563:1494]; - default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd2, m_pipe_enq2Mat_rl[1561:1494] }; endcase end @@ -10793,10 +10780,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3625; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3631; endcase end @@ -10806,10 +10793,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3639; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3645; endcase end @@ -10819,10 +10806,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3653; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3659; endcase end @@ -10832,10 +10819,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3667; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3673; endcase end @@ -10845,10 +10832,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3681; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3687; endcase end @@ -10858,10 +10845,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3695; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3701; endcase end @@ -10871,10 +10858,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3709; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3715; endcase end @@ -10884,10 +10871,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3723; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3729; endcase end @@ -10897,10 +10884,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3737; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3743; endcase end @@ -10910,10 +10897,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3751; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3757; endcase end @@ -10923,10 +10910,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3765; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3771; endcase end @@ -10936,10 +10923,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3779; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3785; endcase end @@ -10949,10 +10936,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3793; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3799; endcase end @@ -10962,10 +10949,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3807; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3813; endcase end @@ -10975,10 +10962,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3821; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3827; endcase end @@ -10988,14 +10975,15 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3835; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3841; endcase end always@(way__h186746 or + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 or @@ -11010,58 +10998,57 @@ module mkLLPipeline(CLK, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 or - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 or - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21) + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20) begin case (way__h186746) 4'd0: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5; 4'd1: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6; 4'd2: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7; 4'd3: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8; 4'd4: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9; 4'd5: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10; 4'd6: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11; 4'd7: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12; 4'd8: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13; 4'd9: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14; 4'd10: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15; 4'd11: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16; 4'd12: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17; 4'd13: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18; 4'd14: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19; 4'd15: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3845 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20; endcase end always@(way__h186746 or @@ -11407,6 +11394,19 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3557; endcase end + always@(send_r) + begin + case (send_r[583:582]) + 2'd0: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { 2'd0, send_r[67:0] }; + 2'd1: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; + default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { 2'd2, send_r[581:518], send_r[3:0] }; + endcase + end // handling of inlined registers diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v index c468cf5..81257fe 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v @@ -25381,75 +25381,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[66]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11078 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11079 or @@ -25519,6 +25450,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11093; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25685,75 +25685,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[64]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11115 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11116 or @@ -25823,6 +25754,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11130; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33423,89 +33423,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[13]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[13]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[13]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[13]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[13]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[13]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[13]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[13]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[13]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[13]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[13]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[13]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[13]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[13]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[13]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[13]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33589,6 +33506,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[12]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[13]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[13]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[13]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[13]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[13]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[13]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[13]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[13]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[13]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[13]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[13]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[13]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[13]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[13]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[13]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[13]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or @@ -33727,89 +33727,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[11]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[11]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[11]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[11]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[11]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[11]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[11]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[11]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[11]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[11]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[11]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[11]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[11]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[11]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[11]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[11]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33893,6 +33810,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[10]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[11]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[11]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[11]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[11]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[11]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[11]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[11]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[11]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[11]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[11]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[11]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[11]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[11]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[11]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[11]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[11]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or @@ -34031,89 +34031,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12147; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[9]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[9]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[9]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[9]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[9]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[9]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[9]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[9]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[9]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[9]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[9]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[9]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[9]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[9]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[9]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[9]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -34197,6 +34114,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[8]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[9]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[9]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[9]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[9]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[9]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[9]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[9]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[9]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[9]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[9]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[9]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[9]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[9]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[9]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[9]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[9]; + endcase + end always@(sendToM_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0850_2188_OR_NOT_ETC___d12192 or NOT_m_reqVec_1_dummy2_0_read__0855_2193_OR_NOT_ETC___d12197 or @@ -34473,6 +34473,73 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0925_AND_m_reqVe_ETC___d12286; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_15_rl[3]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -34607,73 +34674,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[3]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_15_rl[3]; - endcase - end always@(sendToM_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10950 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10951 or @@ -35088,6 +35088,75 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_dummy2_0_read__2379_AND_m_slotVec_ETC___d12419; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; + endcase + end always@(sendToM_getData_n or m_dataValidVec_0_dummy2_0_read__2569_AND_m_dat_ETC___d12574 or m_dataValidVec_1_dummy2_0_read__2575_AND_m_dat_ETC___d12580 or @@ -35157,75 +35226,6 @@ module mkLastLvCRqMshr(CLK, m_dataValidVec_15_dummy2_0_read__2659_AND_m_da_ETC___d12664; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or @@ -35296,72 +35296,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056) + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019; endcase end always@(sendRsToDmaC_getRq_n or @@ -35778,75 +35778,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11167; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11170 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11171 or @@ -35916,6 +35847,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11185; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11207 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11208 or @@ -36192,6 +36192,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11278; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11281 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11282 or @@ -36330,75 +36399,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11337 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11338 or @@ -36675,6 +36675,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11407; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11411 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11412 or @@ -36813,75 +36882,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11463; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11466 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11467 or @@ -37158,75 +37158,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11537; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or @@ -37296,6 +37227,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11577 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11578 or @@ -37779,75 +37779,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11703; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11707 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11708 or @@ -37917,6 +37848,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11722; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11744 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11745 or @@ -38193,6 +38193,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11814; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11818 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11819 or @@ -38262,6 +38331,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11833; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or @@ -38331,75 +38469,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11873 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11874 or @@ -38676,6 +38745,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11944; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11947 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11948 or @@ -38814,75 +38952,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11999; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12003 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12004 or @@ -39159,144 +39228,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092; - endcase - end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or @@ -39366,6 +39297,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12132 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12133 or @@ -39638,6 +39638,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[3]; endcase end + always@(sendRsToDmaC_getData_n or + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673 or + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680 or + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687 or + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694 or + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701 or + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708 or + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715 or + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722 or + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729 or + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736 or + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743 or + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750 or + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757 or + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764 or + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771 or + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778) + begin + case (sendRsToDmaC_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; + endcase + end always@(sendRsToDmaC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10950 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10951 or @@ -39776,75 +39845,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; endcase end - always@(sendRsToDmaC_getData_n or - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673 or - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680 or - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687 or - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694 or - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701 or - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708 or - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715 or - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722 or - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729 or - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736 or - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743 or - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750 or - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757 or - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764 or - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771 or - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778) - begin - case (sendRsToDmaC_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12782 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12784 or @@ -40121,6 +40121,75 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851 or + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853 or + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855 or + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857 or + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859 or + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861 or + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863 or + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865 or + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867 or + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869 or + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871 or + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873 or + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875 or + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877 or + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879 or + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; + endcase + end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12817 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12819 or @@ -40259,75 +40328,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12916; endcase end - always@(sendToM_getData_n or - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851 or - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853 or - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855 or - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857 or - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859 or - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861 or - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863 or - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865 or - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867 or - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869 or - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871 or - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873 or - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875 or - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877 or - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879 or - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881) - begin - case (sendToM_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12920 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12922 or @@ -40604,6 +40604,75 @@ module mkLastLvCRqMshr(CLK, m_dataValidVec_15_dummy2_0_read__2659_AND_m_da_ETC___d12664; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or @@ -40742,75 +40811,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11059 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11060 or @@ -41087,75 +41087,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11130; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11152 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11153 or @@ -41225,6 +41156,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11167; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11170 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11171 or @@ -41708,75 +41708,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11296; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or @@ -41846,6 +41777,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11337 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11338 or @@ -42122,6 +42122,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11407; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11411 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11412 or @@ -42260,75 +42329,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11463; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11466 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11467 or @@ -42605,6 +42605,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11537; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or @@ -42743,75 +42812,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11592; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11596 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11597 or @@ -43088,75 +43088,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11666; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11688 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11689 or @@ -43226,6 +43157,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11703; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11707 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11708 or @@ -43709,75 +43709,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11833; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or @@ -43847,6 +43778,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11873 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11874 or @@ -44123,6 +44123,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11944; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11947 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11948 or @@ -44261,75 +44330,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11999; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12003 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12004 or @@ -44606,6 +44606,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or @@ -44744,75 +44813,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12132 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12133 or @@ -46217,122 +46217,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[65]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[63]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[63]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[63]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[63]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[63]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[63]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[63]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[63]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[63]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[63]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[63]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[63]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[63]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[63]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[63]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[63]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46449,6 +46333,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[64]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[63]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[63]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[63]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[63]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[63]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[63]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[63]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[63]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[63]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[63]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[63]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[63]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[63]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[63]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[63]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[63]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46913,6 +46913,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[59]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[57]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[57]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[57]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[57]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[57]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[57]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[57]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[57]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[57]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[57]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[57]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[57]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[57]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[57]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[57]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[57]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47145,122 +47261,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[56]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[57]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[57]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[57]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[57]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[57]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[57]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[57]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[57]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[57]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[57]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[57]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[57]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[57]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[57]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[57]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[57]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47725,6 +47725,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[52]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[50]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[50]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[50]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[50]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[50]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[50]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[50]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[50]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[50]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[50]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[50]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[50]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[50]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[50]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[50]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[50]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47957,122 +48073,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[49]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[50]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[50]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[50]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[50]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[50]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[50]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[50]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[50]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[50]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[50]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[50]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[50]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[50]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[50]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[50]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[50]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48537,122 +48537,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[45]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[44]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[44]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[44]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[44]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[44]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[44]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[44]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[44]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[44]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[44]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[44]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[44]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[44]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[44]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[44]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[44]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48769,6 +48653,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[43]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[44]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[44]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[44]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[44]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[44]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[44]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[44]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[44]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[44]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[44]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[44]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[44]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[44]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[44]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[44]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[44]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49581,122 +49581,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[36]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[34]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[34]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[34]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[34]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[34]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[34]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[34]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[34]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[34]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[34]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[34]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[34]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[34]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[34]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[34]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[34]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49813,6 +49697,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[35]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[34]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[34]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[34]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[34]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[34]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[34]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[34]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[34]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[34]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[34]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[34]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[34]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[34]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[34]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[34]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[34]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50277,6 +50277,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[30]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[28]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[28]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[28]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[28]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[28]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[28]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[28]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[28]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[28]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[28]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[28]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[28]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[28]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[28]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[28]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[28]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50509,122 +50625,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[27]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[28]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[28]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[28]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[28]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[28]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[28]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[28]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[28]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[28]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[28]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[28]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[28]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[28]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[28]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[28]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[28]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51089,6 +51089,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[23]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[21]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[21]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[21]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[21]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[21]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[21]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[21]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[21]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[21]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[21]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[21]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[21]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[21]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[21]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[21]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[21]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51321,122 +51437,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[20]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[21]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[21]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[21]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[21]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[21]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[21]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[21]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[21]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[21]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[21]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[21]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[21]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[21]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[21]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[21]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[21]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51901,122 +51901,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[16]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[15]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[15]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[15]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[15]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[15]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[15]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[15]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[15]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[15]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[15]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[15]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[15]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[15]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[15]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[15]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[15]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52133,6 +52017,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[14]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[15]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[15]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[15]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[15]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[15]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[15]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[15]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[15]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[15]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[15]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[15]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[15]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[15]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[15]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[15]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[15]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52945,73 +52945,6 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[5]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_15_rl[3]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -53079,6 +53012,73 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_15_rl[3]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -54451,75 +54451,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12166; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12151 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12152 or @@ -54589,6 +54520,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12166; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or @@ -56065,74 +56065,6 @@ module mkLastLvCRqMshr(CLK, n__read_addr__h899290; endcase end - always@(pipelineResp_getRq_n or - n__read_addr__h995902 or - n__read_addr__h996004 or - n__read_addr__h996106 or - n__read_addr__h996208 or - n__read_addr__h996310 or - n__read_addr__h996412 or - n__read_addr__h996514 or - n__read_addr__h996616 or - n__read_addr__h996718 or - n__read_addr__h996820 or - n__read_addr__h996922 or - n__read_addr__h997024 or - n__read_addr__h997126 or - n__read_addr__h997228 or - n__read_addr__h997330 or n__read_addr__h997432) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h995902; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996004; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996106; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996208; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996310; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996412; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996514; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996616; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996718; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996820; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996922; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997024; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997126; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997228; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997330; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997432; - endcase - end always@(sendRqToC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10932 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10933 or @@ -56202,6 +56134,74 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0925_AND_m_reqVe_ETC___d10947; endcase end + always@(pipelineResp_getRq_n or + n__read_addr__h995902 or + n__read_addr__h996004 or + n__read_addr__h996106 or + n__read_addr__h996208 or + n__read_addr__h996310 or + n__read_addr__h996412 or + n__read_addr__h996514 or + n__read_addr__h996616 or + n__read_addr__h996718 or + n__read_addr__h996820 or + n__read_addr__h996922 or + n__read_addr__h997024 or + n__read_addr__h997126 or + n__read_addr__h997228 or + n__read_addr__h997330 or n__read_addr__h997432) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h995902; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996004; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996106; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996208; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996310; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996412; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996514; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996616; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996718; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996820; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996922; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997024; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997126; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997228; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997330; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997432; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -57504,107 +57504,6 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3268; endcase end - always@(transfer_getSlot_n or - m_slotVec_0_dummy2_2$Q_OUT or - IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931 or - m_slotVec_1_dummy2_2$Q_OUT or - IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018 or - m_slotVec_2_dummy2_2$Q_OUT or - IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104 or - m_slotVec_3_dummy2_2$Q_OUT or - IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190 or - m_slotVec_4_dummy2_2$Q_OUT or - IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276 or - m_slotVec_5_dummy2_2$Q_OUT or - IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362 or - m_slotVec_6_dummy2_2$Q_OUT or - IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448 or - m_slotVec_7_dummy2_2$Q_OUT or - IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534 or - m_slotVec_8_dummy2_2$Q_OUT or - IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620 or - m_slotVec_9_dummy2_2$Q_OUT or - IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706 or - m_slotVec_10_dummy2_2$Q_OUT or - IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792 or - m_slotVec_11_dummy2_2$Q_OUT or - IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878 or - m_slotVec_12_dummy2_2$Q_OUT or - IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964 or - m_slotVec_13_dummy2_2$Q_OUT or - IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050 or - m_slotVec_14_dummy2_2$Q_OUT or - IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136 or - m_slotVec_15_dummy2_2$Q_OUT or - IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222) - begin - case (transfer_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_0_dummy2_2$Q_OUT && - IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931; - 4'd1: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_1_dummy2_2$Q_OUT && - IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018; - 4'd2: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_2_dummy2_2$Q_OUT && - IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104; - 4'd3: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_3_dummy2_2$Q_OUT && - IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190; - 4'd4: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_4_dummy2_2$Q_OUT && - IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276; - 4'd5: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_5_dummy2_2$Q_OUT && - IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362; - 4'd6: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_6_dummy2_2$Q_OUT && - IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448; - 4'd7: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_7_dummy2_2$Q_OUT && - IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534; - 4'd8: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_8_dummy2_2$Q_OUT && - IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620; - 4'd9: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_9_dummy2_2$Q_OUT && - IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706; - 4'd10: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_10_dummy2_2$Q_OUT && - IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792; - 4'd11: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_11_dummy2_2$Q_OUT && - IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878; - 4'd12: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_12_dummy2_2$Q_OUT && - IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964; - 4'd13: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_13_dummy2_2$Q_OUT && - IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050; - 4'd14: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_14_dummy2_2$Q_OUT && - IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136; - 4'd15: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_15_dummy2_2$Q_OUT && - IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222; - endcase - end always@(transfer_getSlot_n or m_slotVec_0_dummy2_2$Q_OUT or IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1971 or @@ -57706,6 +57605,107 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3261; endcase end + always@(transfer_getSlot_n or + m_slotVec_0_dummy2_2$Q_OUT or + IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931 or + m_slotVec_1_dummy2_2$Q_OUT or + IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018 or + m_slotVec_2_dummy2_2$Q_OUT or + IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104 or + m_slotVec_3_dummy2_2$Q_OUT or + IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190 or + m_slotVec_4_dummy2_2$Q_OUT or + IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276 or + m_slotVec_5_dummy2_2$Q_OUT or + IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362 or + m_slotVec_6_dummy2_2$Q_OUT or + IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448 or + m_slotVec_7_dummy2_2$Q_OUT or + IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534 or + m_slotVec_8_dummy2_2$Q_OUT or + IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620 or + m_slotVec_9_dummy2_2$Q_OUT or + IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706 or + m_slotVec_10_dummy2_2$Q_OUT or + IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792 or + m_slotVec_11_dummy2_2$Q_OUT or + IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878 or + m_slotVec_12_dummy2_2$Q_OUT or + IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964 or + m_slotVec_13_dummy2_2$Q_OUT or + IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050 or + m_slotVec_14_dummy2_2$Q_OUT or + IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136 or + m_slotVec_15_dummy2_2$Q_OUT or + IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222) + begin + case (transfer_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_0_dummy2_2$Q_OUT && + IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931; + 4'd1: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_1_dummy2_2$Q_OUT && + IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018; + 4'd2: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_2_dummy2_2$Q_OUT && + IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104; + 4'd3: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_3_dummy2_2$Q_OUT && + IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190; + 4'd4: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_4_dummy2_2$Q_OUT && + IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276; + 4'd5: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_5_dummy2_2$Q_OUT && + IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362; + 4'd6: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_6_dummy2_2$Q_OUT && + IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448; + 4'd7: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_7_dummy2_2$Q_OUT && + IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534; + 4'd8: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_8_dummy2_2$Q_OUT && + IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620; + 4'd9: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_9_dummy2_2$Q_OUT && + IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706; + 4'd10: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_10_dummy2_2$Q_OUT && + IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792; + 4'd11: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_11_dummy2_2$Q_OUT && + IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878; + 4'd12: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_12_dummy2_2$Q_OUT && + IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964; + 4'd13: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_13_dummy2_2$Q_OUT && + IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050; + 4'd14: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_14_dummy2_2$Q_OUT && + IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136; + 4'd15: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_15_dummy2_2$Q_OUT && + IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222; + endcase + end always@(transfer_getSlot_n or n__read_repTag__h680626 or n__read_repTag__h680836 or diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v index 49521f0..7a2b298 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v @@ -177,7 +177,6 @@ module mkMemLoader(CLK_portalClk, // inlined wires wire [640 : 0] memReqQ_enqReq_lat_0$wget; - wire memReqQ_enqReq_lat_0$whas; // register busy reg busy; @@ -656,6 +655,7 @@ module mkMemLoader(CLK_portalClk, wire MUX_busy$write_1__SEL_1, MUX_busy$write_1__SEL_2, MUX_expectWrData$write_1__SEL_1, + MUX_pendStCnt$write_1__SEL_2, MUX_writing$write_1__SEL_2; // remaining internal signals @@ -675,13 +675,13 @@ module mkMemLoader(CLK_portalClk, x_wget__h7793; wire [47 : 0] IF_mmio_req_wrBE_BIT_7_67_THEN_mmio_req_wrData_ETC___d1000; wire [31 : 0] IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187, + IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41, IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11, + IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114, IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230, IF_mmio_req_wrBE_BIT_7_67_THEN_mmio_req_wrData_ETC___d993, x__h10090, - x__h1966, x__h3821, - x__h4676, x__h6528; wire [7 : 0] IF_reqSel_70_EQ_0_77_THEN_hostWrDataQ_q_wDataO_ETC___d481, IF_reqSel_70_EQ_1_98_THEN_hostWrDataQ_q_wDataO_ETC___d500, @@ -1317,6 +1317,9 @@ module mkMemLoader(CLK_portalClk, mmio_req_wrBE_BIT_0_60_OR_mmio_req_wrBE_BIT_1__ETC___d978 ; assign MUX_expectWrData$write_1__SEL_1 = WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ; + assign MUX_pendStCnt$write_1__SEL_2 = + WILL_FIRE_RL_doStReq && + reqSel_70_EQ_7_71_OR_hostWrDataQ_q_wDataOut_wg_ETC___d930 ; assign MUX_writing$write_1__SEL_2 = WILL_FIRE_RL_doStResp && pendStCnt == 8'd1 && !expectWrData ; assign MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1 = @@ -1328,7 +1331,7 @@ module mkMemLoader(CLK_portalClk, hostStartQ_q_rWrPtr_rsCounter | x__h6363 : hostStartQ_q_rWrPtr_rsCounter & y__h6550 ; assign MUX_hostWrAddrQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrAddrQ_q_rRdPtr_rsCounter[x__h1966[0]]) ? + (~hostWrAddrQ_q_rRdPtr_rsCounter[IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41[0]]) ? hostWrAddrQ_q_rRdPtr_rsCounter | x__h1801 : hostWrAddrQ_q_rRdPtr_rsCounter & y__h1988 ; assign MUX_hostWrAddrQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1336,7 +1339,7 @@ module mkMemLoader(CLK_portalClk, hostWrAddrQ_q_rWrPtr_rsCounter | x__h938 : hostWrAddrQ_q_rWrPtr_rsCounter & y__h1133 ; assign MUX_hostWrDataQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrDataQ_q_rRdPtr_rsCounter[x__h4676[0]]) ? + (~hostWrDataQ_q_rRdPtr_rsCounter[IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114[0]]) ? hostWrDataQ_q_rRdPtr_rsCounter | x__h4511 : hostWrDataQ_q_rRdPtr_rsCounter & y__h4698 ; assign MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1388,9 +1391,6 @@ module mkMemLoader(CLK_portalClk, IF_reqSel_70_EQ_2_17_THEN_hostWrDataQ_q_wDataO_ETC___d721, IF_reqSel_70_EQ_1_98_THEN_hostWrDataQ_q_wDataO_ETC___d724, IF_reqSel_70_EQ_0_77_THEN_hostWrDataQ_q_wDataO_ETC___d726 } ; - assign memReqQ_enqReq_lat_0$whas = - WILL_FIRE_RL_doStReq && - reqSel_70_EQ_7_71_OR_hostWrDataQ_q_wDataOut_wg_ETC___d930 ; // register busy assign busy$D_IN = !MUX_busy$write_1__SEL_1 ; @@ -1533,7 +1533,7 @@ module mkMemLoader(CLK_portalClk, // register memReqQ_data_0 assign memReqQ_data_0$D_IN = { x_addr__h43806, - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[575:0] : memReqQ_enqReq_rl[575:0] } ; assign memReqQ_data_0$EN = @@ -1568,13 +1568,13 @@ module mkMemLoader(CLK_portalClk, // register pendStCnt always@(MUX_expectWrData$write_1__SEL_1 or - memReqQ_enqReq_lat_0$whas or + MUX_pendStCnt$write_1__SEL_2 or MUX_pendStCnt$write_1__VAL_2 or WILL_FIRE_RL_doStResp or MUX_pendStCnt$write_1__VAL_3) begin case (1'b1) // synopsys parallel_case MUX_expectWrData$write_1__SEL_1: pendStCnt$D_IN = 8'd0; - memReqQ_enqReq_lat_0$whas: + MUX_pendStCnt$write_1__SEL_2: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_2; WILL_FIRE_RL_doStResp: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_3; default: pendStCnt$D_IN = 8'b10101010 /* unspecified value */ ; @@ -1743,7 +1743,7 @@ module mkMemLoader(CLK_portalClk, // submodule memReqQ_enqReq_dummy2_0 assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign memReqQ_enqReq_dummy2_0$EN = memReqQ_enqReq_lat_0$whas ; + assign memReqQ_enqReq_dummy2_0$EN = MUX_pendStCnt$write_1__SEL_2 ; // submodule memReqQ_enqReq_dummy2_1 assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; @@ -1790,16 +1790,24 @@ module mkMemLoader(CLK_portalClk, hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_XOR__ETC___d186 ? 32'd1 : 32'd0 ; + assign IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 = + hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XOR_h_ETC___d40 ? + 32'd1 : + 32'd0 ; assign IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 = hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10 ? 32'd1 : 32'd0 ; + assign IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 = + hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? + 32'd1 : + 32'd0 ; assign IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230 = hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27_XOR_ETC___d229 ? 32'd1 : 32'd0 ; assign IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[640] : memReqQ_enqReq_rl[640] ; assign IF_mmio_req_wrBE_BIT_7_67_THEN_mmio_req_wrData_ETC___d1000 = @@ -2033,7 +2041,7 @@ module mkMemLoader(CLK_portalClk, !memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ; assign NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366 = (!memReqQ_enqReq_dummy2_2$Q_OUT || - (memReqQ_enqReq_lat_0$whas ? + (MUX_pendStCnt$write_1__SEL_2 ? !memReqQ_enqReq_lat_0$wget[640] : !memReqQ_enqReq_rl[640])) && (memReqQ_deqReq_dummy2_2$Q_OUT && @@ -2138,22 +2146,18 @@ module mkMemLoader(CLK_portalClk, 32'd1 : 32'd0 ; assign x__h10885 = x_sReadBin__h10334 + 2'd1 ; - assign x__h1801 = 2'd1 << x__h1966 ; - assign x__h1966 = - hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XOR_h_ETC___d40 ? - 32'd1 : - 32'd0 ; + assign x__h1801 = + 2'd1 << + IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 ; assign x__h2762 = x_sReadBin__h2210 + 2'd1 ; assign x__h3656 = 2'd1 << x__h3821 ; assign x__h3821 = hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? 32'd1 : 32'd0 ; - assign x__h4511 = 2'd1 << x__h4676 ; - assign x__h4676 = - hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? - 32'd1 : - 32'd0 ; + assign x__h4511 = + 2'd1 << + IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 ; assign x__h5470 = x_sReadBin__h4920 + 2'd1 ; assign x__h6363 = 2'd1 << x__h6528 ; assign x__h6528 = @@ -2172,7 +2176,7 @@ module mkMemLoader(CLK_portalClk, IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 ; assign x__h9925 = 2'd1 << x__h10090 ; assign x_addr__h43806 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[639:576] : memReqQ_enqReq_rl[639:576] ; assign x_dReadBin__h10337 = diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index b683294..63491c1 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -1666,60 +1666,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h64161; - reg [63 : 0] v__h64821; - reg [63 : 0] v__h65676; - reg [63 : 0] v__h85257; - reg [63 : 0] v__h85915; - reg [63 : 0] v__h88200; - reg [63 : 0] v__h98637; - reg [63 : 0] v__h99443; - reg [31 : 0] v__h4104; - reg [31 : 0] v__h4270; - reg [31 : 0] v__h4548; - reg [31 : 0] v__h6587; - reg [31 : 0] v__h2380; - reg [31 : 0] v__h6888; - reg [31 : 0] v__h7379; - reg [31 : 0] v__h7542; - reg [31 : 0] v__h139466; - reg [31 : 0] v__h139633; - reg [31 : 0] v__h141736; - reg [31 : 0] v__h159082; - reg [31 : 0] v__h138848; - reg [31 : 0] v__h165777; - reg [31 : 0] v__h166285; - reg [31 : 0] v__h2374; - reg [31 : 0] v__h4098; - reg [31 : 0] v__h4264; - reg [31 : 0] v__h4542; - reg [31 : 0] v__h6581; - reg [31 : 0] v__h6882; - reg [31 : 0] v__h7373; - reg [31 : 0] v__h7536; - reg [31 : 0] v__h138842; - reg [31 : 0] v__h139460; - reg [31 : 0] v__h139627; - reg [31 : 0] v__h141730; - reg [31 : 0] v__h159076; - reg [31 : 0] v__h165771; - reg [31 : 0] v__h166279; + reg [63 : 0] v__h64183; + reg [63 : 0] v__h64843; + reg [63 : 0] v__h65698; + reg [63 : 0] v__h85279; + reg [63 : 0] v__h85937; + reg [63 : 0] v__h88222; + reg [63 : 0] v__h98659; + reg [63 : 0] v__h99465; + reg [31 : 0] v__h4124; + reg [31 : 0] v__h4290; + reg [31 : 0] v__h4568; + reg [31 : 0] v__h6607; + reg [31 : 0] v__h2400; + reg [31 : 0] v__h6908; + reg [31 : 0] v__h7399; + reg [31 : 0] v__h7562; + reg [31 : 0] v__h139488; + reg [31 : 0] v__h139655; + reg [31 : 0] v__h141758; + reg [31 : 0] v__h159104; + reg [31 : 0] v__h138870; + reg [31 : 0] v__h165799; + reg [31 : 0] v__h166307; + reg [31 : 0] v__h2394; + reg [31 : 0] v__h4118; + reg [31 : 0] v__h4284; + reg [31 : 0] v__h4562; + reg [31 : 0] v__h6601; + reg [31 : 0] v__h6902; + reg [31 : 0] v__h7393; + reg [31 : 0] v__h7556; + reg [31 : 0] v__h138864; + reg [31 : 0] v__h139482; + reg [31 : 0] v__h139649; + reg [31 : 0] v__h141752; + reg [31 : 0] v__h159098; + reg [31 : 0] v__h165793; + reg [31 : 0] v__h166301; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x2164_0_n__read_addr2342_1_n__read_addr24_ETC__q26, - CASE_x3161_0_n__read_addr3343_1_n__read_addr34_ETC__q15, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x2186_0_n__read_addr2364_1_n__read_addr24_ETC__q26, + CASE_x3183_0_n__read_addr3365_1_n__read_addr34_ETC__q15, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087, @@ -1729,34 +1729,34 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145, IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113, IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115, - data64__h152906, - ld_data__h135927, - w1__h49460, - w1__h49465, - w2__h49461, - w2__h49467, - x__h49456; + data64__h152928, + ld_data__h135949, + w1__h49482, + w1__h49487, + w2__h49483, + w2__h49489, + x__h49478; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1211; - reg [7 : 0] strb8__h152907; + reg [7 : 0] strb8__h152929; reg [5 : 0] IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_ETC___d608; - reg [2 : 0] x__h63475; - reg [1 : 0] CASE_x2164_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, - CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14; + reg [2 : 0] x__h63497; + reg [1 : 0] CASE_x2186_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, + CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x2164_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x3161_0_propDstData_0_dummy2_1_read__325__ETC__q12, + CASE_x2186_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x3183_0_propDstData_0_dummy2_1_read__325__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_IF_ETC___d1318, SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_AND__ETC___d1633, - x__h63482, - x__h84580; + x__h63504, + x__h84602; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1584; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1583; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725, - new_cline__h139769; + new_cline__h139791; wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708; wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674; @@ -1777,84 +1777,84 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_1_ETC___d781, IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1469, IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1507, - data__h30994, - failed_testnum__h167675, - mem_req_rd_addr_araddr__h139067, - mem_req_wr_addr_awaddr__h152991, - mmioPlatform_fromHostQ_data_0__h42898, - mmioPlatform_mtime__h36831, - mmioPlatform_reqData__h50052, - n__read_addr__h63343, - n__read_addr__h63428, - n__read_addr__h82342, - n__read_addr__h82421, - n__read_snd_addr__h97990, - newData__h31076, - newData__h34526, - op_result__h50068, - op_result__h50598, - op_result__h50603, - op_result__h50608, - op_result__h50613, - op_result__h50619, - op_result__h50626, - op_result__h50632, - result__h49511, - result__h49635, - result__h49663, - result__h49691, - result__h49719, - result__h49747, - result__h49775, - result__h49803, - result__h49831, - result__h49876, - result__h49904, - result__h49932, - result__h49960, - result__h50001, - result__h50029, - result__h50155, - result__h50182, - result__h50209, - result__h50236, - result__h50263, - result__h50290, - result__h50317, - result__h50344, - result__h50388, - result__h50415, - result__h50442, - result__h50469, - result__h50509, - result__h50536, - result__h50653, - result__h50719, - result__h50785, - result__h50851, - result__h50917, - result__h50983, - result__h51049, - result__h51111, - result__h51156, - result__h51222, - result__h51288, - result__h51346, - result__h51391, - value__h38063, - w1___1__h49570, - w2___1__h49571, - x1_avValue_data__h40554, - x1_avValue_data__h40564, - x1_avValue_data__h45256, - x1_avValue_data__h45266, - x__h31187, - x__h34617, - x__h41088, - x__h41099, - x__h43181, - x__h43192, - x__h51568; + data__h31017, + failed_testnum__h167693, + mem_req_rd_addr_araddr__h139089, + mem_req_wr_addr_awaddr__h153013, + mmioPlatform_fromHostQ_data_0__h42920, + mmioPlatform_mtime__h36854, + mmioPlatform_reqData__h50074, + n__read_addr__h63365, + n__read_addr__h63450, + n__read_addr__h82364, + n__read_addr__h82443, + n__read_snd_addr__h98012, + newData__h31099, + newData__h34549, + op_result__h50090, + op_result__h50620, + op_result__h50625, + op_result__h50630, + op_result__h50635, + op_result__h50641, + op_result__h50648, + op_result__h50654, + result__h49533, + result__h49657, + result__h49685, + result__h49713, + result__h49741, + result__h49769, + result__h49797, + result__h49825, + result__h49853, + result__h49898, + result__h49926, + result__h49954, + result__h49982, + result__h50023, + result__h50051, + result__h50177, + result__h50204, + result__h50231, + result__h50258, + result__h50285, + result__h50312, + result__h50339, + result__h50366, + result__h50410, + result__h50437, + result__h50464, + result__h50491, + result__h50531, + result__h50558, + result__h50675, + result__h50741, + result__h50807, + result__h50873, + result__h50939, + result__h51005, + result__h51071, + result__h51133, + result__h51178, + result__h51244, + result__h51310, + result__h51368, + result__h51413, + value__h38086, + w1___1__h49592, + w2___1__h49593, + x1_avValue_data__h40576, + x1_avValue_data__h40586, + x1_avValue_data__h45278, + x1_avValue_data__h45288, + x__h31210, + x__h34640, + x__h41110, + x__h41121, + x__h43203, + x__h43214, + x__h51590; wire [47 : 0] IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d675, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d748, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d865; @@ -1862,22 +1862,22 @@ module mkProc(CLK, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d666, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d743, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d860, - lower_data__h30931, + lower_data__h30954, mmioPlatform_mtime_BITS_31_TO_0__q4, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - upper_data__h30932, - v__h30787, - v__h30824, - w19460_BITS_31_TO_0__q7, - w29461_BITS_31_TO_0__q8, - x_data__h29573; + upper_data__h30955, + v__h30810, + v__h30847, + w19482_BITS_31_TO_0__q7, + w29483_BITS_31_TO_0__q8, + x_data__h29596; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389; - wire [5 : 0] x__h139102, x__h153016; + wire [5 : 0] x__h139124, x__h153038; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388; - wire [3 : 0] b__h138775, b__h2274; - wire [2 : 0] n__read_id__h63347, n__read_id__h63432; + wire [3 : 0] b__h138797, b__h2294; + wire [2 : 0] n__read_id__h63369, n__read_id__h63454; wire [1 : 0] IF_enqDst_0_lat_0_whas__263_THEN_enqDst_0_lat__ETC___d1415, IF_enqDst_0_lat_0_whas__263_THEN_enqDst_0_lat__ETC___d1426, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1560, @@ -1967,22 +1967,22 @@ module mkProc(CLK, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d452, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d474, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d524, - mmioPlatform_reqBE_BIT_0___h29198, - mmioPlatform_reqBE_BIT_4___h29158, + mmioPlatform_reqBE_BIT_0___h29221, + mmioPlatform_reqBE_BIT_4___h29181, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d593, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d702, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d775, mmioPlatform_toHostQ_enqReq_dummy2_2_read__04__ETC___d216, - n__read_child__h63348, - n__read_child__h63433, - n__read_child__h82345, - n__read_child__h82424, - n__read_snd_id__h97991, + n__read_child__h63370, + n__read_child__h63455, + n__read_child__h82367, + n__read_child__h82446, + n__read_snd_id__h98013, propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361, propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365, - x__h63161, - x__h77093, - x__h82164; + x__h63183, + x__h77115, + x__h82186; // action method hart0_server_reset_request_put assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -1997,7 +1997,7 @@ module mkProc(CLK, EN_hart0_server_reset_response_get ; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = CAN_FIRE_start ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; @@ -2992,13 +2992,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2274 == 4'd0 ; + b__h2294 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2274 != 4'd0 && + b__h2294 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3110,7 +3110,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h43181 == 64'd0 || + x__h43203 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3287,13 +3287,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h138775 == 4'd0 ; + b__h138797 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h138775 != 4'd0 && + b__h138797 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3301,8 +3301,8 @@ module mkProc(CLK, CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = WILL_FIRE_RL_rl_reset ; - assign WILL_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = @@ -3385,7 +3385,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h29573 } ; + x_data__h29596 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 && @@ -3420,7 +3420,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__85__ETC___d1216 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h30994 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31017 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3527,7 +3527,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h49456 } ; + x__h49478 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_ETC___d608, @@ -3536,52 +3536,52 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h51568, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h51590, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { 1'd1, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43181 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43203 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h43181 != 64'd0 ; + x__h43203 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41088 == 64'd0 ; + x__h41110 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63161 ; + x__h63183 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x3161_0_n__read_addr3343_1_n__read_addr34_ETC__q15, + CASE_x3183_0_n__read_addr3365_1_n__read_addr34_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82164 ; + x__h82186 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x2164_0_n__read_addr2342_1_n__read_addr24_ETC__q26, + CASE_x2186_0_n__read_addr2364_1_n__read_addr24_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732 } ; assign enqDst_0_lat_0_1$wget = - { 1'd1, n__read_snd_addr__h97990, n__read_snd_id__h97991 } ; + { 1'd1, n__read_snd_addr__h98012, n__read_snd_id__h98013 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -3630,13 +3630,13 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2274 - 4'd1 ; + b__h2294 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2274 ; + b__h2294 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - WILL_FIRE_RL_rl_reset ? + CAN_FIRE_RL_rl_reset ? 4'd0 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = @@ -3687,13 +3687,13 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h138775 - 4'd1 ; + b__h138797 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h138775 ; + b__h138797 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - WILL_FIRE_RL_rl_reset ? + CAN_FIRE_RL_rl_reset ? 4'd0 : llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; @@ -3766,7 +3766,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h139067, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h139089, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -3777,13 +3777,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h152991, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h153013, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h152906, strb8__h152907, 1'd1 } ; + { 4'd0, data64__h152928, strb8__h152929, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -3795,7 +3795,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h139769 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h139791 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3932,7 +3932,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h34526 : + newData__h34549 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -3941,7 +3941,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h31076 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h31099 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4363,7 +4363,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h135927, llc$dma_respLd_first[3] } ; + { ld_data__h135949, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4500,7 +4500,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1581 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h139769, + { new_cline__h139791, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -4760,55 +4760,55 @@ module mkProc(CLK, assign tlbQ$CLR = 1'b0 ; // remaining internal signals - module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29158 && - mmioPlatform_reqBE_BIT_0___h29198, - 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h36831), - .amoExec_in_data(mmioPlatform_reqData__h50052), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29158 && - !mmioPlatform_reqBE_BIT_0___h29198), - .amoExec(x__h34617)); module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29158 && - mmioPlatform_reqBE_BIT_0___h29198, + mmioPlatform_reqBE_BIT_4___h29181 && + mmioPlatform_reqBE_BIT_0___h29221, 2'd0 }), - .amoExec_current_data(value__h38063), - .amoExec_in_data(mmioPlatform_reqData__h50052), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29158 && - !mmioPlatform_reqBE_BIT_0___h29198), - .amoExec(x__h31187)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29158 && - mmioPlatform_reqBE_BIT_0___h29198, + .amoExec_current_data(value__h38086), + .amoExec_in_data(mmioPlatform_reqData__h50074), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29181 && + !mmioPlatform_reqBE_BIT_0___h29221), + .amoExec(x__h31210)); + module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h29181 && + mmioPlatform_reqBE_BIT_0___h29221, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42898), - .amoExec_in_data(mmioPlatform_reqData__h50052), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29158 && - !mmioPlatform_reqBE_BIT_0___h29198), - .amoExec(x__h41099)); + .amoExec_current_data(mmioPlatform_mtime__h36854), + .amoExec_in_data(mmioPlatform_reqData__h50074), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29181 && + !mmioPlatform_reqBE_BIT_0___h29221), + .amoExec(x__h34640)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29158 && - mmioPlatform_reqBE_BIT_0___h29198, + mmioPlatform_reqBE_BIT_4___h29181 && + mmioPlatform_reqBE_BIT_0___h29221, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h50052), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29158 && - !mmioPlatform_reqBE_BIT_0___h29198), - .amoExec(x__h43192)); + .amoExec_in_data(mmioPlatform_reqData__h50074), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29181 && + !mmioPlatform_reqBE_BIT_0___h29221), + .amoExec(x__h43214)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h29181 && + mmioPlatform_reqBE_BIT_0___h29221, + 2'd0 }), + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42920), + .amoExec_in_data(mmioPlatform_reqData__h50074), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29181 && + !mmioPlatform_reqBE_BIT_0___h29221), + .amoExec(x__h41121)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_66_BIT_ETC___d831 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h40554 } } ; + x1_avValue_data__h40576 } } ; assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_66_BIT_ETC___d879 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { IF_mmioPlatform_fromHostQ_empty_00_THEN_IF_NOT_ETC___d873, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h45256 } } ; + x1_avValue_data__h45278 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4__ETC___d690 = (IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 && !mmioPlatform_mtip_0 || @@ -4831,7 +4831,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 = - newData__h31076 <= mmioPlatform_mtime ; + newData__h31099 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__287_288_OR__ETC___d1322 = NOT_propDstIdx_0_dummy2_1_read__287_288_OR_IF__ETC___d1321 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -4910,7 +4910,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, - x__h77093 } ; + x__h77115 } ; assign IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1584 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -4933,8 +4933,8 @@ module mkProc(CLK, SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1211 ; assign IF_mmioPlatform_fromHostQ_empty_00_THEN_IF_NOT_ETC___d873 = mmioPlatform_fromHostQ_empty ? - x__h43181 == 64'd0 : - x__h41088 == 64'd0 ; + x__h43203 == 64'd0 : + x__h41110 == 64'd0 ; assign IF_mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioP_ETC___d764 = ((mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d755 && !mmioPlatform_mtip_0) ? @@ -5063,8 +5063,8 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_2_ETC___d891 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h43181 != 64'd0 : - x__h41088 != 64'd0) : + x__h43203 != 64'd0 : + x__h41110 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__54__ETC___d163 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? @@ -5316,38 +5316,38 @@ module mkProc(CLK, !propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389 = - { CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, - CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14, + { CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, + CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732 = - { CASE_x2164_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x2164_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x2186_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x2186_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725, - x__h84580 } ; + x__h84602 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674 = - { CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388 = - { CASE_x3161_0_propDstData_0_dummy2_1_read__325__ETC__q12, - x__h63475, - x__h63482 } ; - assign b__h138775 = + { CASE_x3183_0_propDstData_0_dummy2_1_read__325__ETC__q12, + x__h63497, + x__h63504 } ; + assign b__h138797 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2274 = + assign b__h2294 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -5396,22 +5396,22 @@ module mkProc(CLK, !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345) && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350 ; - assign data__h30994 = + assign data__h31017 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h30787, 32'd0 } ; - assign failed_testnum__h167675 = + { v__h30810, 32'd0 } ; + assign failed_testnum__h167693 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign lower_data__h30931 = - mmioPlatform_waitLowerMSIPCRs ? v__h30824 : 32'd0 ; - assign mem_req_rd_addr_araddr__h139067 = - { llc$to_mem_toM_first[68:11], x__h139102 } ; - assign mem_req_wr_addr_awaddr__h152991 = - { llc$to_mem_toM_first[639:582], x__h153016 } ; + assign lower_data__h30954 = + mmioPlatform_waitLowerMSIPCRs ? v__h30847 : 32'd0 ; + assign mem_req_rd_addr_araddr__h139089 = + { llc$to_mem_toM_first[68:11], x__h139124 } ; + assign mem_req_wr_addr_awaddr__h153013 = + { llc$to_mem_toM_first[639:582], x__h153038 } ; assign mmioPlatform_cycle_10_ULT_99___d311 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_195_ULT_mmioPlatform__ETC___d1204 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h42898 = + assign mmioPlatform_fromHostQ_data_0__h42920 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d294 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -5422,9 +5422,9 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h36831 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h36854 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d755 = - mmioPlatform_mtimecmp_0 <= newData__h34526 ; + mmioPlatform_mtimecmp_0 <= newData__h34549 ; assign mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = @@ -5525,9 +5525,9 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_notEmpty && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d343 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345 ; - assign mmioPlatform_reqBE_BIT_0___h29198 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h29158 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h50052 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h29221 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h29181 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h50074 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d593 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -5554,104 +5554,104 @@ module mkProc(CLK, !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h63343 = + assign n__read_addr__h63365 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h63428 = + assign n__read_addr__h63450 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h82342 = + assign n__read_addr__h82364 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1469 : 64'd0 ; - assign n__read_addr__h82421 = + assign n__read_addr__h82443 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1507 : 64'd0 ; - assign n__read_child__h63348 = + assign n__read_child__h63370 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h63433 = + assign n__read_child__h63455 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h82345 = + assign n__read_child__h82367 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1495 ; - assign n__read_child__h82424 = + assign n__read_child__h82446 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1533 ; - assign n__read_id__h63347 = + assign n__read_id__h63369 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h63432 = + assign n__read_id__h63454 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h97990 = + assign n__read_snd_addr__h98012 = propDstData_0_dummy2_1_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[64:1] : propDstData_0_rl_1[64:1]) : 64'd0 ; - assign n__read_snd_id__h97991 = + assign n__read_snd_id__h98013 = propDstData_0_dummy2_1_1$Q_OUT && (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[0] : propDstData_0_rl_1[0]) ; - assign newData__h31076 = + assign newData__h31099 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h31187 : + x__h31210 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d683 ; - assign newData__h34526 = + assign newData__h34549 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h34617 : + x__h34640 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d753 ; - assign new_cline__h139769 = + assign new_cline__h139791 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h50068 = + assign op_result__h50090 = IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 + IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ; - assign op_result__h50598 = w1__h49465 ^ w2__h49467 ; - assign op_result__h50603 = w1__h49465 & w2__h49467 ; - assign op_result__h50608 = w1__h49465 | w2__h49467 ; - assign op_result__h50613 = - (w1__h49465 < w2__h49467) ? w1__h49465 : w2__h49467 ; - assign op_result__h50619 = - (w1__h49465 <= w2__h49467) ? w2__h49467 : w1__h49465 ; - assign op_result__h50626 = + assign op_result__h50620 = w1__h49487 ^ w2__h49489 ; + assign op_result__h50625 = w1__h49487 & w2__h49489 ; + assign op_result__h50630 = w1__h49487 | w2__h49489 ; + assign op_result__h50635 = + (w1__h49487 < w2__h49489) ? w1__h49487 : w2__h49489 ; + assign op_result__h50641 = + (w1__h49487 <= w2__h49489) ? w2__h49489 : w1__h49487 ; + assign op_result__h50648 = ((IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ^ 64'h8000000000000000)) ? - w1__h49465 : - w2__h49467 ; - assign op_result__h50632 = + w1__h49487 : + w2__h49489 ; + assign op_result__h50654 = ((IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ^ 64'h8000000000000000)) ? - w2__h49467 : - w1__h49465 ; + w2__h49489 : + w1__h49487 ; assign propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -5662,130 +5662,130 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h49511 = + assign result__h49533 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0] } ; - assign result__h49635 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h49663 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h49691 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h49719 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h49747 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h49775 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h49803 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h49831 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h49876 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h49904 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h49932 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h49960 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h50001 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h50029 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h50155 = + assign result__h49657 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h49685 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h49713 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h49741 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h49769 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h49797 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h49825 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h49853 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h49898 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h49926 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h49954 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h49982 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h50023 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h50051 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h50177 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h50182 = + assign result__h50204 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h50209 = + assign result__h50231 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h50236 = + assign result__h50258 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h50263 = + assign result__h50285 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h50290 = + assign result__h50312 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h50317 = + assign result__h50339 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h50344 = + assign result__h50366 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h50388 = + assign result__h50410 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h50415 = + assign result__h50437 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h50442 = + assign result__h50464 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h50469 = + assign result__h50491 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h50509 = + assign result__h50531 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h50536 = + assign result__h50558 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h50653 = + assign result__h50675 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h50719 = + assign result__h50741 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h50785 = + assign result__h50807 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h50851 = + assign result__h50873 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h50917 = + assign result__h50939 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h50983 = + assign result__h51005 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h51049 = + assign result__h51071 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h51111 = + assign result__h51133 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0] } ; - assign result__h51156 = + assign result__h51178 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h51222 = + assign result__h51244 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h51288 = + assign result__h51310 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h51346 = + assign result__h51368 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[31:0] } ; - assign result__h51391 = + assign result__h51413 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[31:0], mmioPlatform_reqData[31:0] } ; - assign upper_data__h30932 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h30787 ; - assign v__h30787 = mmioPlatform_waitUpperMSIPCRs ? v__h30824 : 32'd0 ; - assign v__h30824 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign value__h38063 = mmioPlatform_mtimecmp_0 ; - assign w19460_BITS_31_TO_0__q7 = w1__h49460[31:0] ; - assign w1___1__h49570 = { 32'd0, w1__h49460[31:0] } ; - assign w29461_BITS_31_TO_0__q8 = w2__h49461[31:0] ; - assign w2___1__h49571 = { 32'd0, w2__h49461[31:0] } ; - assign x1_avValue_data__h40554 = x1_avValue_data__h40564 ; - assign x1_avValue_data__h40564 = + assign upper_data__h30955 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h30810 ; + assign v__h30810 = mmioPlatform_waitUpperMSIPCRs ? v__h30847 : 32'd0 ; + assign v__h30847 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign value__h38086 = mmioPlatform_mtimecmp_0 ; + assign w19482_BITS_31_TO_0__q7 = w1__h49482[31:0] ; + assign w1___1__h49592 = { 32'd0, w1__h49482[31:0] } ; + assign w29483_BITS_31_TO_0__q8 = w2__h49483[31:0] ; + assign w2___1__h49593 = { 32'd0, w2__h49483[31:0] } ; + assign x1_avValue_data__h40576 = x1_avValue_data__h40586 ; + assign x1_avValue_data__h40586 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h45256 = x1_avValue_data__h45266 ; - assign x1_avValue_data__h45266 = + assign x1_avValue_data__h45278 = x1_avValue_data__h45288 ; + assign x1_avValue_data__h45288 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h139102 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h153016 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h41088 = + assign x__h139124 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h153038 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h41110 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h41099 : + x__h41121 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d870 ; - assign x__h43181 = + assign x__h43203 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h43192 : + x__h43214 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -5794,123 +5794,123 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h51568 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h63161 = + assign x__h51590 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h63183 = SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_IF_ETC___d1318 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__287_288_OR_IF__ETC___d1321 ; - assign x__h77093 = + assign x__h77115 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1581 ; - assign x__h82164 = + assign x__h82186 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_AND__ETC___d1633 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__592_593_OR_I_ETC___d1636 ; - assign x_data__h29573 = { 31'd0, mmioPlatform_reqData[0] } ; + assign x_data__h29596 = { 31'd0, mmioPlatform_reqData[0] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h135927 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h135927 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h135927 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h135927 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h135927 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h135927 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h135927 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h135927 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h135949 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h135949 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h135949 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h135949 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h135949 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h135949 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h135949 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h135949 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h152906 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h152906 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h152906 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h152906 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h152906 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h152906 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h152906 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h152906 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h152928 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h152928 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h152928 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h152928 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h152928 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h152928 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h152928 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h152928 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h152907 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h152907 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h152907 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h152907 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h152907 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h152907 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h152907 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h152907 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h152929 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h152929 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h152929 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h152929 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h152929 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h152929 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h152929 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h152929 = llc$to_mem_toM_first[575:568]; endcase end always@(mmioPlatform_curReq or - result__h49635 or - result__h49663 or - result__h49691 or - result__h49719 or - result__h49747 or - result__h49775 or result__h49803 or result__h49831) + result__h49657 or + result__h49685 or + result__h49713 or + result__h49741 or + result__h49769 or + result__h49797 or result__h49825 or result__h49853) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49635; + result__h49657; 3'h1: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49663; + result__h49685; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49691; + result__h49713; 3'h3: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49719; + result__h49741; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49747; + result__h49769; 3'h5: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49775; + result__h49797; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49803; + result__h49825; 3'h7: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h49831; + result__h49853; endcase end always@(mmioPlatform_curReq or - result__h49876 or - result__h49904 or result__h49932 or result__h49960) + result__h49898 or + result__h49926 or result__h49954 or result__h49982) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h49876; + result__h49898; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h49904; + result__h49926; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h49932; + result__h49954; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h49960; + result__h49982; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h50001 or result__h50029) + always@(mmioPlatform_curReq or result__h50023 or result__h50051) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h50001; + result__h50023; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h50029; + result__h50051; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -5922,102 +5922,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h49461 = + w2__h49483 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035; 2'b01: - w2__h49461 = + w2__h49483 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; 2'b10: - w2__h49461 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h49483 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h49461 = + w2__h49483 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 or - w2___1__h49571 or + w2___1__h49593 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055) begin case (mmioPlatform_reqSz) 2'b0: - w2__h49467 = + w2__h49489 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035; 2'b01: - w2__h49467 = + w2__h49489 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; - 2'b10: w2__h49467 = w2___1__h49571; + 2'b10: w2__h49489 = w2___1__h49593; 2'b11: - w2__h49467 = + w2__h49489 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_curReq or - result__h50388 or - result__h50415 or result__h50442 or result__h50469) + result__h50177 or + result__h50204 or + result__h50231 or + result__h50258 or + result__h50285 or + result__h50312 or result__h50339 or result__h50366) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50177; + 3'h1: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50204; + 3'h2: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50231; + 3'h3: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50258; + 3'h4: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50285; + 3'h5: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50312; + 3'h6: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50339; + 3'h7: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = + result__h50366; + endcase + end + always@(mmioPlatform_curReq or + result__h50410 or + result__h50437 or result__h50464 or result__h50491) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h50388; + result__h50410; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h50415; + result__h50437; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h50442; + result__h50464; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h50469; + result__h50491; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h50155 or - result__h50182 or - result__h50209 or - result__h50236 or - result__h50263 or - result__h50290 or result__h50317 or result__h50344) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50155; - 3'h1: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50182; - 3'h2: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50209; - 3'h3: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50236; - 3'h4: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50263; - 3'h5: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50290; - 3'h6: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50317; - 3'h7: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50344; - endcase - end - always@(mmioPlatform_curReq or result__h50509 or result__h50536) + always@(mmioPlatform_curReq or result__h50531 or result__h50558) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h50509; + result__h50531; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h50536; + result__h50558; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -6029,41 +6029,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h49460 = + w1__h49482 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087; 2'b01: - w1__h49460 = + w1__h49482 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; 2'b10: - w1__h49460 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h49482 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h49460 = + w1__h49482 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 or - w1___1__h49570 or + w1___1__h49592 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106) begin case (mmioPlatform_reqSz) 2'b0: - w1__h49465 = + w1__h49487 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087; 2'b01: - w1__h49465 = + w1__h49487 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; - 2'b10: w1__h49465 = w1___1__h49570; + 2'b10: w1__h49487 = w1___1__h49592; 2'b11: - w1__h49465 = + w1__h49487 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 or - w19460_BITS_31_TO_0__q7 or + w19482_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106) begin case (mmioPlatform_reqSz) @@ -6075,7 +6075,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; 2'b10: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 = - { {32{w19460_BITS_31_TO_0__q7[31]}}, w19460_BITS_31_TO_0__q7 }; + { {32{w19482_BITS_31_TO_0__q7[31]}}, w19482_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; @@ -6084,7 +6084,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 or - w29461_BITS_31_TO_0__q8 or + w29483_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055) begin case (mmioPlatform_reqSz) @@ -6096,115 +6096,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; 2'b10: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 = - { {32{w29461_BITS_31_TO_0__q8[31]}}, w29461_BITS_31_TO_0__q8 }; + { {32{w29483_BITS_31_TO_0__q8[31]}}, w29483_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h50632 or - w2__h49467 or - op_result__h50068 or - op_result__h50598 or - op_result__h50603 or - op_result__h50608 or - op_result__h50626 or op_result__h50613 or op_result__h50619) + op_result__h50654 or + w2__h49489 or + op_result__h50090 or + op_result__h50620 or + op_result__h50625 or + op_result__h50630 or + op_result__h50648 or op_result__h50635 or op_result__h50641) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - w2__h49467; + w2__h49489; 4'd1: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50068; + op_result__h50090; 4'd2: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50598; + op_result__h50620; 4'd3: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50603; + op_result__h50625; 4'd4: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50608; + op_result__h50630; 4'd5: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50626; + op_result__h50648; 4'd7: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50613; + op_result__h50635; 4'd8: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50619; + op_result__h50641; default: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50632; + op_result__h50654; endcase end always@(mmioPlatform_curReq or - result__h51111 or - result__h51156 or result__h51222 or result__h51288) + result__h51133 or + result__h51178 or result__h51244 or result__h51310) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51111; + result__h51133; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51156; + result__h51178; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51222; + result__h51244; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51288; + result__h51310; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h49511 or - result__h50653 or - result__h50719 or - result__h50785 or - result__h50851 or - result__h50917 or result__h50983 or result__h51049) + result__h49533 or + result__h50675 or + result__h50741 or + result__h50807 or + result__h50873 or + result__h50939 or result__h51005 or result__h51071) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h49511; + result__h49533; 3'h1: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50653; + result__h50675; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50719; + result__h50741; 3'h3: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50785; + result__h50807; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50851; + result__h50873; 3'h5: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50917; + result__h50939; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50983; + result__h51005; 3'h7: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51049; + result__h51071; endcase end - always@(mmioPlatform_curReq or result__h51346 or result__h51391) + always@(mmioPlatform_curReq or result__h51368 or result__h51413) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h51346; + result__h51368; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h51391; + result__h51413; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -6216,15 +6216,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h49456 = + x__h49478 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169; 2'b01: - x__h49456 = + x__h49478 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178; 2'b10: - x__h49456 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h49478 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h49456 = + x__h49478 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end @@ -6308,278 +6308,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__456_THEN_propDst_ETC___d1459; endcase end - always@(x__h63161 or n__read_id__h63347 or n__read_id__h63432) + always@(x__h63183 or n__read_id__h63369 or n__read_id__h63454) begin - case (x__h63161) - 1'd0: x__h63475 = n__read_id__h63347; - 1'd1: x__h63475 = n__read_id__h63432; + case (x__h63183) + 1'd0: x__h63497 = n__read_id__h63369; + 1'd1: x__h63497 = n__read_id__h63454; endcase end - always@(x__h63161 or n__read_child__h63348 or n__read_child__h63433) + always@(x__h63183 or n__read_child__h63370 or n__read_child__h63455) begin - case (x__h63161) - 1'd0: x__h63482 = n__read_child__h63348; - 1'd1: x__h63482 = n__read_child__h63433; + case (x__h63183) + 1'd0: x__h63504 = n__read_child__h63370; + 1'd1: x__h63504 = n__read_child__h63455; endcase end - always@(x__h63161 or + always@(x__h63183 or propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361 or propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365) begin - case (x__h63161) + case (x__h63183) 1'd0: - CASE_x3161_0_propDstData_0_dummy2_1_read__325__ETC__q12 = + CASE_x3183_0_propDstData_0_dummy2_1_read__325__ETC__q12 = propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361; 1'd1: - CASE_x3161_0_propDstData_0_dummy2_1_read__325__ETC__q12 = + CASE_x3183_0_propDstData_0_dummy2_1_read__325__ETC__q12 = propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365; endcase end - always@(x__h63161 or + always@(x__h63183 or IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1341 or IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1345) begin - case (x__h63161) + case (x__h63183) 1'd0: - CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = + CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1341; 1'd1: - CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = + CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1345; endcase end - always@(x__h63161 or + always@(x__h63183 or IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1351 or IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1355) begin - case (x__h63161) + case (x__h63183) 1'd0: - CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = + CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1351; 1'd1: - CASE_x3161_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = + CASE_x3183_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1355; endcase end - always@(x__h63161 or n__read_addr__h63343 or n__read_addr__h63428) + always@(x__h63183 or n__read_addr__h63365 or n__read_addr__h63450) begin - case (x__h63161) + case (x__h63183) 1'd0: - CASE_x3161_0_n__read_addr3343_1_n__read_addr34_ETC__q15 = - n__read_addr__h63343; + CASE_x3183_0_n__read_addr3365_1_n__read_addr34_ETC__q15 = + n__read_addr__h63365; 1'd1: - CASE_x3161_0_n__read_addr3343_1_n__read_addr34_ETC__q15 = - n__read_addr__h63428; + CASE_x3183_0_n__read_addr3365_1_n__read_addr34_ETC__q15 = + n__read_addr__h63450; endcase end - always@(x__h82164 or n__read_child__h82345 or n__read_child__h82424) + always@(x__h82186 or n__read_child__h82367 or n__read_child__h82446) begin - case (x__h82164) - 1'd0: x__h84580 = n__read_child__h82345; - 1'd1: x__h84580 = n__read_child__h82424; + case (x__h82186) + 1'd0: x__h84602 = n__read_child__h82367; + 1'd1: x__h84602 = n__read_child__h82446; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h82164 or + always@(x__h82186 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x2164_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x2186_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h82164 or + always@(x__h82186 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1474 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1512) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x2186_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1474 : 2'd0; 1'd1: - CASE_x2164_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x2186_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1512 : 2'd0; endcase end - always@(x__h82164 or + always@(x__h82186 or NOT_propDstData_1_0_dummy2_1_read__640_651_OR__ETC___d1652 or NOT_propDstData_1_1_dummy2_1_read__642_653_OR__ETC___d1654) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x2186_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__640_651_OR__ETC___d1652; 1'd1: - CASE_x2164_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x2186_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__642_653_OR__ETC___d1654; endcase end - always@(x__h82164 or n__read_addr__h82342 or n__read_addr__h82421) + always@(x__h82186 or n__read_addr__h82364 or n__read_addr__h82443) begin - case (x__h82164) + case (x__h82186) 1'd0: - CASE_x2164_0_n__read_addr2342_1_n__read_addr24_ETC__q26 = - n__read_addr__h82342; + CASE_x2186_0_n__read_addr2364_1_n__read_addr24_ETC__q26 = + n__read_addr__h82364; 1'd1: - CASE_x2164_0_n__read_addr2342_1_n__read_addr24_ETC__q26 = - n__read_addr__h82421; + CASE_x2186_0_n__read_addr2364_1_n__read_addr24_ETC__q26 = + n__read_addr__h82443; endcase end @@ -6981,13 +6981,13 @@ module mkProc(CLK, if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394) begin - v__h64161 = $time; + v__h64183 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394) - $display("%t XBar %m: deq src %d", v__h64161, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h64183, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394 && @@ -7005,39 +7005,39 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63161) + x__h63183) begin - v__h64821 = $time; + v__h64843 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63161) - $display("%t XBar %m: deq src %d", v__h64821, $signed(32'd1)); + x__h63183) + $display("%t XBar %m: deq src %d", v__h64843, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63161 && + x__h63183 && NOT_propDstIdx_1_dummy2_1_read__300_301_OR_IF__ETC___d1403) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63161 && + x__h63183 && NOT_propDstIdx_1_dummy2_1_read__300_301_OR_IF__ETC___d1403) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 120, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63161 && + x__h63183 && NOT_propDstIdx_1_dummy2_1_read__300_301_OR_IF__ETC___d1403) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) begin - v__h65676 = $time; + v__h65698 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) - $write("%t XBAR %m: enq dst %d ; ", v__h65676, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h65698, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) $write("CRqMsg { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) @@ -7126,13 +7126,13 @@ module mkProc(CLK, if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737) begin - v__h85257 = $time; + v__h85279 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737) - $display("%t XBar %m: deq src %d", v__h85257, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h85279, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737 && @@ -7150,39 +7150,39 @@ module mkProc(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82164) + x__h82186) begin - v__h85915 = $time; + v__h85937 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82164) - $display("%t XBar %m: deq src %d", v__h85915, $signed(32'd1)); + x__h82186) + $display("%t XBar %m: deq src %d", v__h85937, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82164 && + x__h82186 && NOT_propDstIdx_1_1_dummy2_1_read__610_611_OR_I_ETC___d1745) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82164 && + x__h82186 && NOT_propDstIdx_1_1_dummy2_1_read__610_611_OR_I_ETC___d1745) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 120, column 53\nsrc must be proposing"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82164 && + x__h82186 && NOT_propDstIdx_1_1_dummy2_1_read__610_611_OR_I_ETC___d1745) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) begin - v__h88200 = $time; + v__h88222 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) - $write("%t XBAR %m: enq dst %d ; ", v__h88200, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h88222, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) $write("CRsMsg { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) @@ -7352,12 +7352,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875) begin - v__h98637 = $time; + v__h98659 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875) - $display("%t XBar %m: deq src %d", v__h98637, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h98659, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875 && !CAN_FIRE_RL_srcPropose_4 && @@ -7366,12 +7366,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) begin - v__h99443 = $time; + v__h99465 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) - $write("%t XBAR %m: enq dst %d ; ", v__h99443, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h99465, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) $write("<"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) $write("'h%h", 1'd0); @@ -7723,7 +7723,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sendLdRespToTlb) $write("TlbLdResp { ", "data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sendLdRespToTlb) $write("'h%h", ld_data__h135927); + if (WILL_FIRE_RL_sendLdRespToTlb) $write("'h%h", ld_data__h135949); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sendLdRespToTlb) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) @@ -7794,7 +7794,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h167675); + $display("FAIL %0d", failed_testnum__h167693); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -7802,14 +7802,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4104 = $stime; + v__h4124 = $stime; #0; end - v__h4098 = v__h4104 / 32'd10; + v__h4118 = v__h4124 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4098); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4118); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7868,15 +7868,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4270 = $stime; + v__h4290 = $stime; #0; end - v__h4264 = v__h4270 / 32'd10; + v__h4284 = v__h4290 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h4264); + v__h4284); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -7965,15 +7965,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4548 = $stime; + v__h4568 = $stime; #0; end - v__h4542 = v__h4548 / 32'd10; + v__h4562 = v__h4568 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4542); + v__h4562); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8142,14 +8142,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6587 = $stime; + v__h6607 = $stime; #0; end - v__h6581 = v__h6587 / 32'd10; + v__h6601 = v__h6607 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6581); + $display("%0d: ERROR: CreditCounter: overflow", v__h6601); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -8302,15 +8302,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2380 = $stime; + v__h2400 = $stime; #0; end - v__h2374 = v__h2380 / 32'd10; + v__h2394 = v__h2400 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2374); + v__h2394); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8575,14 +8575,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6888 = $stime; + v__h6908 = $stime; #0; end - v__h6882 = v__h6888 / 32'd10; + v__h6902 = v__h6908 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6882); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6902); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8619,15 +8619,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7379 = $stime; + v__h7399 = $stime; #0; end - v__h7373 = v__h7379 / 32'd10; + v__h7393 = v__h7399 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7373); + v__h7393); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -8667,14 +8667,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7542 = $stime; + v__h7562 = $stime; #0; end - v__h7536 = v__h7542 / 32'd10; + v__h7556 = v__h7562 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7536); + v__h7556); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9360,8 +9360,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h30931, - upper_data__h30932); + lower_data__h30954, + upper_data__h30955); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -9428,7 +9428,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d720) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h31076, "\n"); + $write(", new mtimecmp[%d] %x", 1'd0, newData__h31099, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -9508,7 +9508,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d791) - $write(", new mtime %x", newData__h34526, ", mtimecmp "); + $write(", new mtime %x", newData__h34549, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d791) @@ -9628,7 +9628,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) - $write("'h%h", x1_avValue_data__h40564, " }"); + $write("'h%h", x1_avValue_data__h40586, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) @@ -9641,37 +9641,37 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43181 != 64'd0) + x__h43203 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43181 != 64'd0) + x__h43203 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 856, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43181 != 64'd0) + x__h43203 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41088 != 64'd0) + x__h41110 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41088 != 64'd0) + x__h41110 != 64'd0) $display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 848, column 41\nCan only write 0 to fromhost"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41088 != 64'd0) + x__h41110 != 64'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -9718,7 +9718,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) - $write("'h%h", x1_avValue_data__h45266, " }"); + $write("'h%h", x1_avValue_data__h45288, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) @@ -10026,7 +10026,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", x__h51568); + $write("'h%h", x__h51590); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -10147,15 +10147,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) begin - v__h139466 = $stime; + v__h139488 = $stime; #0; end - v__h139460 = v__h139466 / 32'd10; + v__h139482 = v__h139488 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h139460, + v__h139482, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -10215,15 +10215,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h139633 = $stime; + v__h139655 = $stime; #0; end - v__h139627 = v__h139633 / 32'd10; + v__h139649 = v__h139655 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h139627); + v__h139649); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10404,16 +10404,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h141736 = $stime; + v__h141758 = $stime; #0; end - v__h141730 = v__h141736 / 32'd10; + v__h141752 = v__h141758 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h141730); + v__h141752); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11611,14 +11611,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h159082 = $stime; + v__h159104 = $stime; #0; end - v__h159076 = v__h159082 / 32'd10; + v__h159098 = v__h159104 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h159076); + $display("%0d: ERROR: CreditCounter: overflow", v__h159098); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11642,7 +11642,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", mem_req_wr_addr_awaddr__h152991); + $write("'h%h", mem_req_wr_addr_awaddr__h153013); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -11738,7 +11738,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", data64__h152906); + $write("'h%h", data64__h152928); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -11746,7 +11746,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", strb8__h152907); + $write("'h%h", strb8__h152929); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -11772,16 +11772,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h138848 = $stime; + v__h138870 = $stime; #0; end - v__h138842 = v__h138848 / 32'd10; + v__h138864 = v__h138870 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h138842, + v__h138864, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11869,7 +11869,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", mem_req_rd_addr_araddr__h139067); + $write("'h%h", mem_req_rd_addr_araddr__h139089); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -11950,15 +11950,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) begin - v__h165777 = $stime; + v__h165799 = $stime; #0; end - v__h165771 = v__h165777 / 32'd10; + v__h165793 = v__h165799 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h165771, + v__h165793, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -11996,15 +11996,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h166285 = $stime; + v__h166307 = $stime; #0; end - v__h166279 = v__h166285 / 32'd10; + v__h166301 = v__h166307 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h166279); + v__h166301); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v index bfa61a2..e633a5b 100644 --- a/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v +++ b/builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v @@ -20,7 +20,7 @@ // set_verbosity_logdelay I 64 unused // to_raw_mem_response_put I 256 // put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg +// set_watch_tohost_watch_tohost I 1 // set_watch_tohost_tohost_addr I 64 reg // EN_set_verbosity I 1 // EN_to_raw_mem_response_put I 1 @@ -178,6 +178,8 @@ module mkSoC_Top(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, + corew$set_htif_addrs_fromhost_addr, + corew$set_htif_addrs_tohost_addr, corew$set_verbosity_logdelay; wire [7 : 0] corew$cpu_dmem_master_arlen, corew$cpu_dmem_master_awlen, @@ -226,6 +228,7 @@ module mkSoC_Top(CLK, corew$cpu_imem_master_rresp; wire corew$EN_cpu_reset_server_request_put, corew$EN_cpu_reset_server_response_get, + corew$EN_set_htif_addrs, corew$EN_set_verbosity, corew$RDY_cpu_reset_server_request_put, corew$RDY_cpu_reset_server_response_get, @@ -677,12 +680,15 @@ module mkSoC_Top(CLK, WILL_FIRE_to_raw_mem_request_get, WILL_FIRE_to_raw_mem_response_put; + // inputs to muxes for submodule ports + wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; + // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h8706; - reg [31 : 0] v__h8966; - reg [31 : 0] v__h8700; - reg [31 : 0] v__h8960; + reg [31 : 0] v__h8723; + reg [31 : 0] v__h8983; + reg [31 : 0] v__h8717; + reg [31 : 0] v__h8977; // synopsys translate_on // action method set_verbosity @@ -811,12 +817,16 @@ module mkSoC_Top(CLK, .cpu_imem_master_rvalid(corew$cpu_imem_master_rvalid), .cpu_imem_master_wready(corew$cpu_imem_master_wready), .debug_external_interrupt_req_set_not_clear(corew$debug_external_interrupt_req_set_not_clear), + .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), + .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .EN_set_verbosity(corew$EN_set_verbosity), + .EN_set_htif_addrs(corew$EN_set_htif_addrs), .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), .RDY_set_verbosity(), + .RDY_set_htif_addrs(), .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), @@ -1344,21 +1354,26 @@ module mkSoC_Top(CLK, assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; // rule RL_rl_reset_start_2 - assign CAN_FIRE_RL_rl_reset_start_2 = - fabric$RDY_reset && corew$RDY_cpu_reset_server_request_put && - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start_2 = CAN_FIRE_RL_rl_reset_start_2 ; + assign CAN_FIRE_RL_rl_reset_start_2 = MUX_rg_state$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_reset_start_2 = MUX_rg_state$write_1__SEL_1 ; // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - corew$RDY_cpu_reset_server_response_get && + assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ; + assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ; + + // inputs to muxes for submodule ports + assign MUX_rg_state$write_1__SEL_1 = + mem0_controller$RDY_server_reset_request_put && + uart0$RDY_server_reset_request_put && + fabric$RDY_reset && + corew$RDY_cpu_reset_server_request_put && + rg_state == 2'd0 ; + assign MUX_rg_state$write_1__SEL_2 = + mem0_controller$RDY_set_addr_map && mem0_controller$RDY_server_reset_response_get && uart0$RDY_server_reset_response_get && - mem0_controller$RDY_set_addr_map && + corew$RDY_cpu_reset_server_response_get && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = CAN_FIRE_RL_rl_reset_complete ; // register rg_state assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_2 ? 2'd1 : 2'd2 ; @@ -1397,7 +1412,7 @@ module mkSoC_Top(CLK, assign boot_rom$slave_wlast = fabric$v_to_slaves_0_wlast ; assign boot_rom$slave_wstrb = fabric$v_to_slaves_0_wstrb ; assign boot_rom$slave_wvalid = fabric$v_to_slaves_0_wvalid ; - assign boot_rom$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; // submodule corew assign corew$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = @@ -1455,13 +1470,16 @@ module mkSoC_Top(CLK, assign corew$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; assign corew$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; assign corew$debug_external_interrupt_req_set_not_clear = 1'd0 ; + assign corew$set_htif_addrs_fromhost_addr = 64'd0 ; + assign corew$set_htif_addrs_tohost_addr = set_watch_tohost_tohost_addr ; assign corew$set_verbosity_logdelay = set_verbosity_logdelay ; assign corew$set_verbosity_verbosity = set_verbosity_verbosity ; assign corew$EN_set_verbosity = EN_set_verbosity ; - assign corew$EN_cpu_reset_server_request_put = - CAN_FIRE_RL_rl_reset_start_2 ; + assign corew$EN_set_htif_addrs = + EN_set_watch_tohost && set_watch_tohost_watch_tohost ; + assign corew$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; assign corew$EN_cpu_reset_server_response_get = - CAN_FIRE_RL_rl_reset_complete ; + MUX_rg_state$write_1__SEL_2 ; // submodule fabric assign fabric$set_verbosity_verbosity = 4'h0 ; @@ -1556,7 +1574,7 @@ module mkSoC_Top(CLK, assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = CAN_FIRE_RL_rl_reset_start_2 ; + assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; assign fabric$EN_set_verbosity = 1'b0 ; // submodule mem0_controller @@ -1599,10 +1617,10 @@ module mkSoC_Top(CLK, assign mem0_controller$slave_wvalid = fabric$v_to_slaves_1_wvalid ; assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; assign mem0_controller$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start_2 ; + MUX_rg_state$write_1__SEL_1 ; assign mem0_controller$EN_server_reset_response_get = - CAN_FIRE_RL_rl_reset_complete ; - assign mem0_controller$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + MUX_rg_state$write_1__SEL_2 ; + assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; assign mem0_controller$EN_to_raw_mem_request_get = EN_to_raw_mem_request_get ; assign mem0_controller$EN_to_raw_mem_response_put = @@ -1647,9 +1665,9 @@ module mkSoC_Top(CLK, assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start_2 ; - assign uart0$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_complete ; - assign uart0$EN_set_addr_map = CAN_FIRE_RL_rl_reset_complete ; + assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; + assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; + assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; assign uart0$EN_get_to_console_get = EN_get_to_console_get ; assign uart0$EN_put_from_console_put = EN_put_from_console_put ; @@ -1686,23 +1704,23 @@ module mkSoC_Top(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_start_2) begin - v__h8706 = $stime; + v__h8723 = $stime; #0; end - v__h8700 = v__h8706 / 32'd10; + v__h8717 = v__h8723 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_start_2) - $display("%0d: SoC_Top. Reset start ...", v__h8700); + $display("%0d: SoC_Top. Reset start ...", v__h8717); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete) begin - v__h8966 = $stime; + v__h8983 = $stime; #0; end - v__h8960 = v__h8966 / 32'd10; + v__h8977 = v__h8983 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete) - $display("%0d: SoC_Top. Reset complete ...", v__h8960); + $display("%0d: SoC_Top. Reset complete ...", v__h8977); end // synopsys translate_on endmodule // mkSoC_Top diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index 039c007..6cf6d60 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -27,12 +27,13 @@ package Proc; // ================================================================ // BSV lib imports -import Vector::*; -import GetPut::*; -import ClientServer::*; -import Connectable::*; -import FIFOF :: *; -import ConfigReg :: *; +import Assert :: *; +import Vector :: *; +import GetPut :: *; +import ClientServer :: *; +import Connectable :: *; +import FIFOF :: *; +import ConfigReg :: *; // ---------------- // BSV additional libs @@ -65,15 +66,17 @@ import Performance::*; import ISA_Decls :: *; -import AXI4_Types :: *; -import Fabric_Defs :: *; - import Core :: *; import Proc_IFC :: *; import MMIOPlatform :: *; import LLC_AXI4_Adapter :: *; import MMIO_AXI4_Adapter :: *; +import SoC_Map :: *; +import AXI4_Types :: *; +import Fabric_Defs :: *; + + `ifdef INCLUDE_GDB_CONTROL import DM_CPU_Req_Rsp :: *; `endif @@ -86,6 +89,12 @@ import TV_Info :: *; (* synthesize *) module mkProc (Proc_IFC); + + // Check that RISCY-OOO and Bluespec defs of boot rom size are the same + staticAssert ( (soc_map_struct.boot_rom_addr_size == fromInteger (valueOf (TExp #(LgBootRomBytes)))), + "Boot ROM size def mismatch: ProcConfig.bsv:LgBootRomBytes vs. SoC_Map.bsv:soc_map_struct.boot_rom_addr_size"); + + // ---------------- // cores Vector#(CoreNum, Core) core = ?; for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index e7cced6..71d8290 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -98,6 +98,10 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); Debug_Module_IFC debug_module <- mkDebug_Module; `endif + // HTIF locations (for debugging only) + Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0); + Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0); + // ================================================================ // RESET // There are two sources of reset requests to the CPU: externally @@ -159,10 +163,9 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); f_reset_rsps.enq (?); // Start running the cores - Bit #(64) startpc = 'h_0000_1000; // TODO: fixup - Bit #(64) tohostAddr = 'h_8000_1000; // TODO: fixup - Bit #(64) fromhostAddr = 0; - proc.start (startpc, tohostAddr, fromhostAddr); + proc.start (soc_map_struct.pc_reset_value, + rg_tohost_addr, + rg_fromhost_addr); $display ("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", cur_cycle); endrule @@ -334,13 +337,18 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources)); // INTERFACE // ---------------------------------------------------------------- - // Debugging: set core's verbosity + // Debugging: set core's verbosity, htif addrs method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); // Warning: ignoring logdelay proc.set_verbosity (verbosity); endmethod + method Action set_htif_addrs (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + rg_tohost_addr <= tohost_addr; + rg_fromhost_addr <= fromhost_addr; + endmethod + // ---------------------------------------------------------------- // Soft reset diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv index c6cfe69..84b2968 100644 --- a/src_Core/Core/CoreW_IFC.bsv +++ b/src_Core/Core/CoreW_IFC.bsv @@ -46,10 +46,12 @@ import Debug_Module :: *; interface CoreW_IFC #(numeric type t_n_interrupt_sources); // ---------------------------------------------------------------- - // Debugging: set core's verbosity + // Debugging: set core's verbosity, htif addrs method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); + method Action set_htif_addrs (Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + // ---------------------------------------------------------------- // Soft reset diff --git a/src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv b/src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv index 84eac2d..97a0675 100644 --- a/src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv @@ -25,6 +25,8 @@ import Types::*; import ProcTypes::*; import CCTypes::*; +import SoC_Map :: *; // Bluespec setup + // data aligned addr typedef TSub#(AddrSz, LgDataSzBytes) DataAlignedAddrSz; typedef Bit#(DataAlignedAddrSz) DataAlignedAddr; @@ -32,12 +34,20 @@ typedef Bit#(DataAlignedAddrSz) DataAlignedAddr; function DataAlignedAddr getDataAlignedAddr(Addr a) = truncateLSB(a); // base addr for each MMIO reg/device (aligned to Data) +/* ORIGINAL MIT SETUP DataAlignedAddr bootRomBaseAddr = getDataAlignedAddr(64'h00001000); DataAlignedAddr memLoaderBaseAddr = getDataAlignedAddr(64'h01000000); DataAlignedAddr msipBaseAddr = getDataAlignedAddr(64'h02000000); DataAlignedAddr mtimecmpBaseAddr = getDataAlignedAddr(64'h02004000); DataAlignedAddr mtimeBaseAddr = getDataAlignedAddr(64'h0200bff8); DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(64'h80000000); +*/ + +DataAlignedAddr bootRomBaseAddr = getDataAlignedAddr(soc_map_struct.boot_rom_addr_base); +DataAlignedAddr msipBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_0000); +DataAlignedAddr mtimecmpBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_4000); +DataAlignedAddr mtimeBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_bff8); +DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(soc_map_struct.mem0_controller_addr_base); // XXX Each msip reg is 32-bit, while mtime and each mtimecmp are 64-bit. We // assume Data is 64-bit. We hard code this relation in all MMIO logic. @@ -50,7 +60,6 @@ DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(64'h80000000); // (aligned to Data) DataAlignedAddr bootRomBoundAddr = bootRomBaseAddr + fromInteger(valueof(TExp#(LgBootRomSzData))); -DataAlignedAddr memLoaderBoundAddr = memLoaderBaseAddr + 2; DataAlignedAddr msipBoundAddr = msipBaseAddr + fromInteger(valueof(TDiv#(CoreNum, 2))); DataAlignedAddr mtimecmpBoundAddr = mtimecmpBaseAddr + diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 2646d16..306423f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -3967,7 +3967,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3, @@ -4056,7 +4056,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_4, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, @@ -4317,8 +4317,8 @@ module mkCore(CLK, reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0001__ETC__q221, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255, CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q251, CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q252, IF_checkForException_0207_BIT_4_0208_THEN_IF_c_ETC___d20909, @@ -6023,7 +6023,7 @@ module mkCore(CLK, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21514, NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21565, - NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708, + NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708, NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_deq_ETC___d25186, NOT_rob_deqPort_0_deq_data__3972_BITS_122_TO_1_ETC___d24474, NOT_rob_deqPort_1_deq_data__4676_BIT_25_4677_4_ETC___d24705, @@ -6526,8 +6526,8 @@ module mkCore(CLK, csrf_prv_reg_read__0001_ULE_1_4341_AND_IF_comm_ETC___d24381, csrf_prv_reg_read__0001_ULE_1___d24341, fetchStage_RDY_pipelines_0_first__9968_AND_NOT_ETC___d21158, + fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022, fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21220, - fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d21732, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d22237, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d22360, @@ -6582,7 +6582,7 @@ module mkCore(CLK, next_deqP___1__h401670, next_deqP___1__h404895, r__h697623, - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584, + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584, regRenamingTable_RDY_rename_1_getRename__1640__ETC___d21658, regRenamingTable_rename_0_canRename__1142_AND__ETC___d21215, regRenamingTable_rename_0_canRename__1142_AND__ETC___d21469, @@ -6721,7 +6721,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23120, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23187, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23472, - rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022, + rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712, specTagManager_canClaim__1140_AND_regRenamingT_ETC___d21875, specTagManager_canClaim__1140_AND_regRenamingT_ETC___d22170, v__h371968, @@ -9696,9 +9696,9 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && + l2Tlb$RDY_toChildren_rqFromC_put && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && - l2Tlb$RDY_toChildren_rqFromC_put ; + coreFix_memExe_dTlb$RDY_toParent_rqToP_first ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq @@ -9711,24 +9711,24 @@ module mkCore(CLK, // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = - coreFix_memExe_dTlb$RDY_toParent_flush_request_get && - l2Tlb$RDY_toChildren_dTlbReqFlush_put ; + l2Tlb$RDY_toChildren_dTlbReqFlush_put && + coreFix_memExe_dTlb$RDY_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; // rule RL_mkConnectionGetPut_1 @@ -9740,8 +9740,8 @@ module mkCore(CLK, // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - coreFix_memExe_dTlb$RDY_toParent_flush_response_put && l2Tlb$RDY_toChildren_flushDone_get && + coreFix_memExe_dTlb$RDY_toParent_flush_response_put && fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; @@ -10083,7 +10083,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_commitTrap[133] && @@ -10133,8 +10133,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[103] && rob$deqPort_0_deq_data[18] ; @@ -10214,7 +10214,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708 && + NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[103] && !rob$deqPort_0_deq_data[18] && @@ -10365,8 +10365,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10377,8 +10377,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10452,16 +10452,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -10472,8 +10472,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10511,8 +10511,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10609,8 +10609,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10627,8 +10627,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10650,8 +10650,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10798,8 +10798,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -10862,8 +10862,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11090,8 +11090,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11129,9 +11129,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + epochManager$RDY_incrementEpoch && fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty && epochManager$checkEpoch_0_check && fetchStage_pipelines_0_first__9971_BIT_4_0000__ETC___d20210 && @@ -11144,7 +11145,7 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022 && + fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d21037 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11495,7 +11496,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; assign MUX_rf$write_3_wr_2__SEL_5 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -11986,12 +11987,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[98:96] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : @@ -17506,24 +17507,24 @@ module mkCore(CLK, coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPredPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -17719,16 +17720,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -22473,10 +22474,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__9971_BITS_98__ETC___d21597 = IF_fetchStage_pipelines_0_first__9971_BITS_98__ETC___d21590 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[98:96] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__9971_BIT_4_00_ETC___d21005 = @@ -22509,10 +22510,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d21677 && IF_fetchStage_RDY_pipelines_1_first__9979_AND__ETC___d21491 && (IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d21702 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712) ; + regRenamingTable$RDY_rename_1_claimRename && + rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712) ; assign IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d23959 = (fetchStage$pipelines_1_first[98:96] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__9969_9970_O_ETC___d22617 && @@ -24542,12 +24543,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_216_AND_rob_RDY_se_ETC___d1217 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_216_AND_rob_RDY_se_ETC___d1606 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -24619,10 +24620,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[4] || checkForException___d20207[4] || !rob$enqPort_0_canEnq ; - assign NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708 = + assign NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__4676_BIT_25_4677_4_ETC___d24705) ; @@ -24660,7 +24661,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[122:118] == 5'd15 || rob$deqPort_1_deq_data[122:118] == 5'd19 || rob$deqPort_1_deq_data[122:118] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21643 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21514 || @@ -31191,7 +31192,7 @@ module mkCore(CLK, !coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2202 && !coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2205 ; assign coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2200 = - coreFix_memExe_dTlb$procResp[174:114] < 61'd268435456 ; + coreFix_memExe_dTlb$procResp[174:114] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2202 = coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ; assign coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2205 = @@ -31293,9 +31294,9 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__098_AND_coreFix_me_ETC___d24479 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__3972_BITS_122_TO_1_ETC___d24474 ; @@ -31368,6 +31369,14 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__9971_BITS_10_ETC___d21155 ; + assign fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022 = + fetchStage$RDY_pipelines_0_first && + fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[98:96] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21220 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[98:96] == 3'd1 && @@ -31375,12 +31384,6 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__9968_AND__ETC___d21162 ; - assign fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21708) && - (fetchStage$pipelines_1_first[98:96] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d21732 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__9971_BITS_98_ETC___d21729 && @@ -32215,7 +32218,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] % coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ; assign r__h697623 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584 = + assign regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_95_TO_9_ETC__q227 && (fetchStage$pipelines_0_first[103:99] == 5'd14 || @@ -33607,14 +33610,12 @@ module mkCore(CLK, guard__h660917 } ; assign result__h740783 = w__h740778 & y__h740812 ; assign result__h740834 = ~x__h740833 ; - assign rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[98:96] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21708) && + (fetchStage$pipelines_1_first[98:96] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__3972_BITS_186_TO_123_3_ETC___d24641 = rob$deqPort_0_deq_data[186:123] + 64'd4 ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q253 = @@ -39453,7 +39454,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__9971_BITS_95__ETC___d21237 or - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584 or + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1165_co_ETC___d21175 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__9971_BI_ETC___d21572 or @@ -39475,7 +39476,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[98:96] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__9971_BITS_95__ETC___d21237 || - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584; + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584; endcase end always@(fetchStage$pipelines_0_first or @@ -39915,39 +39916,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or - IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or - IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802 or - IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839 or - IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875 or - IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912 or - IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948 or - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or - IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 or - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) - 3'd0, 3'd2, 3'd4: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; - 3'd1: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - { IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766, - IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802, - IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839, - IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875, - IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912, - IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948, - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985, - IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 }; - 3'd3: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729; - default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839 or @@ -39992,28 +39960,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) - 3'd0, 3'd2, 3'd4: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - 3'd1: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985; - 3'd3: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912 or @@ -40058,6 +40004,28 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) + 3'd0, 3'd2, 3'd4: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + 3'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985; + 3'd3: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or @@ -40120,6 +40088,39 @@ module mkCore(CLK, 3'd0; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or + IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or + IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802 or + IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839 or + IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875 or + IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912 or + IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948 or + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or + IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 or + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) + 3'd0, 3'd2, 3'd4: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; + 3'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + { IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766, + IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802, + IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839, + IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875, + IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912, + IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948, + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985, + IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 }; + 3'd3: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -40394,28 +40395,6 @@ module mkCore(CLK, { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -40432,9 +40411,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256 = 4'd15; endcase end diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index f1c4192..45250cf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -7,6 +7,7 @@ // Ports: // Name I/O size props // RDY_set_verbosity O 1 const +// RDY_set_htif_addrs O 1 const // RDY_cpu_reset_server_request_put O 1 reg // RDY_cpu_reset_server_response_get O 1 reg // cpu_imem_master_awvalid O 1 @@ -78,6 +79,8 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// set_htif_addrs_tohost_addr I 64 reg +// set_htif_addrs_fromhost_addr I 64 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 @@ -121,6 +124,7 @@ // dm_dmi_write_dm_addr I 7 // dm_dmi_write_dm_word I 32 // EN_set_verbosity I 1 +// EN_set_htif_addrs I 1 // EN_cpu_reset_server_request_put I 1 // EN_cpu_reset_server_response_get I 1 // EN_dm_dmi_read_addr I 1 @@ -159,6 +163,11 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, + set_htif_addrs_tohost_addr, + set_htif_addrs_fromhost_addr, + EN_set_htif_addrs, + RDY_set_htif_addrs, + EN_cpu_reset_server_request_put, RDY_cpu_reset_server_request_put, @@ -375,6 +384,12 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; + // action method set_htif_addrs + input [63 : 0] set_htif_addrs_tohost_addr; + input [63 : 0] set_htif_addrs_fromhost_addr; + input EN_set_htif_addrs; + output RDY_set_htif_addrs; + // action method cpu_reset_server_request_put input EN_cpu_reset_server_request_put; output RDY_cpu_reset_server_request_put; @@ -738,6 +753,7 @@ module mkCoreW(CLK, RDY_dm_dmi_read_data, RDY_dm_dmi_write, RDY_dm_ndm_reset_req_get_get, + RDY_set_htif_addrs, RDY_set_verbosity, RDY_tv_verifier_info_get_get, cpu_dmem_master_arlock, @@ -757,6 +773,16 @@ module mkCoreW(CLK, cpu_imem_master_wlast, cpu_imem_master_wvalid; + // register rg_fromhost_addr + reg [63 : 0] rg_fromhost_addr; + wire [63 : 0] rg_fromhost_addr$D_IN; + wire rg_fromhost_addr$EN; + + // register rg_tohost_addr + reg [63 : 0] rg_tohost_addr; + wire [63 : 0] rg_tohost_addr$D_IN; + wire rg_tohost_addr$EN; + // ports of submodule debug_module wire [76 : 0] debug_module$hart0_csr_mem_client_request_get; wire [69 : 0] debug_module$hart0_gpr_mem_client_request_get; @@ -1452,6 +1478,7 @@ module mkCoreW(CLK, CAN_FIRE_dm_dmi_read_data, CAN_FIRE_dm_dmi_write, CAN_FIRE_dm_ndm_reset_req_get_get, + CAN_FIRE_set_htif_addrs, CAN_FIRE_set_verbosity, CAN_FIRE_tv_verifier_info_get_get, WILL_FIRE_RL_ClientServerRequest, @@ -1533,17 +1560,18 @@ module mkCoreW(CLK, WILL_FIRE_dm_dmi_read_data, WILL_FIRE_dm_dmi_write, WILL_FIRE_dm_ndm_reset_req_get_get, + WILL_FIRE_set_htif_addrs, WILL_FIRE_set_verbosity, WILL_FIRE_tv_verifier_info_get_get; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h4698; - reg [31 : 0] v__h4872; - reg [31 : 0] v__h5141; - reg [31 : 0] v__h4692; - reg [31 : 0] v__h4866; - reg [31 : 0] v__h5135; + reg [31 : 0] v__h4766; + reg [31 : 0] v__h4940; + reg [31 : 0] v__h5210; + reg [31 : 0] v__h4760; + reg [31 : 0] v__h4934; + reg [31 : 0] v__h5204; // synopsys translate_on // remaining internal signals @@ -1554,6 +1582,11 @@ module mkCoreW(CLK, assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; + // action method set_htif_addrs + assign RDY_set_htif_addrs = 1'd1 ; + assign CAN_FIRE_set_htif_addrs = 1'd1 ; + assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; + // action method cpu_reset_server_request_put assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; @@ -2639,29 +2672,29 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - dm_gpr_tap_ifc$RDY_client_request_get && - proc$RDY_hart0_gpr_mem_server_request_put ; + proc$RDY_hart0_gpr_mem_server_request_put && + dm_gpr_tap_ifc$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - dm_gpr_tap_ifc$RDY_client_response_put && - proc$RDY_hart0_gpr_mem_server_response_get ; + proc$RDY_hart0_gpr_mem_server_response_get && + dm_gpr_tap_ifc$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -2674,29 +2707,29 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; // rule RL_ClientServerRequest_4 assign CAN_FIRE_RL_ClientServerRequest_4 = - dm_csr_tap$RDY_client_request_get && - proc$RDY_hart0_csr_mem_server_request_put ; + proc$RDY_hart0_csr_mem_server_request_put && + dm_csr_tap$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_4 = CAN_FIRE_RL_ClientServerRequest_4 ; // rule RL_ClientServerResponse_4 assign CAN_FIRE_RL_ClientServerResponse_4 = - dm_csr_tap$RDY_client_response_put && - proc$RDY_hart0_csr_mem_server_response_get ; + proc$RDY_hart0_csr_mem_server_response_get && + dm_csr_tap$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_4 = CAN_FIRE_RL_ClientServerResponse_4 ; @@ -2817,8 +2850,9 @@ module mkCoreW(CLK, // rule RL_rl_cpu_hart0_reset_from_dm_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && + plic$RDY_server_reset_request_put && debug_module$RDY_hart0_get_reset_req_get && + fabric_2x3$RDY_reset && proc$RDY_hart0_server_reset_request_put && f_reset_requestor$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = @@ -2842,6 +2876,14 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; + // register rg_fromhost_addr + assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; + assign rg_fromhost_addr$EN = EN_set_htif_addrs ; + + // register rg_tohost_addr + assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; + assign rg_tohost_addr$EN = EN_set_htif_addrs ; + // submodule debug_module assign debug_module$dmi_read_addr_dm_addr = dm_dmi_read_addr_dm_addr ; assign debug_module$dmi_write_dm_addr = dm_dmi_write_dm_addr ; @@ -3228,9 +3270,9 @@ module mkCoreW(CLK, assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = 64'd0 ; - assign proc$start_startpc = 64'h0000000000001000 ; - assign proc$start_tohostAddr = 64'h0000000080001000 ; + assign proc$start_fromhostAddr = rg_fromhost_addr ; + assign proc$start_startpc = 64'h0000000070000000 ; + assign proc$start_tohostAddr = rg_tohost_addr ; assign proc$EN_hart0_server_reset_request_put = WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; @@ -3274,6 +3316,35 @@ module mkCoreW(CLK, f_reset_reqs$EMPTY_N && f_reset_requestor$FULL_N ; + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + end + else + begin + if (rg_fromhost_addr$EN) + rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; + if (rg_tohost_addr$EN) + rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; + rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + // handling of system tasks // synopsys translate_off @@ -3283,34 +3354,34 @@ module mkCoreW(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin - v__h4698 = $stime; + v__h4766 = $stime; #0; end - v__h4692 = v__h4698 / 32'd10; + v__h4760 = v__h4766 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4692); + $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4760); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) begin - v__h4872 = $stime; + v__h4940 = $stime; #0; end - v__h4866 = v__h4872 / 32'd10; + v__h4934 = v__h4940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h4866); + $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h4934); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) begin - v__h5141 = $stime; + v__h5210 = $stime; #0; end - v__h5135 = v__h5141 / 32'd10; + v__h5204 = v__h5210 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h5135); + v__h5204); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v index 19f6de0..905234d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v @@ -2694,7 +2694,7 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q187, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q49, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q51, @@ -2733,7 +2733,7 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q32, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q33, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q34; - reg CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183, + reg CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184, CASE_n__read22512_0_NOT_instdata_data_0_BIT_32_ETC__q206, CASE_n__read22512_0_NOT_instdata_data_0_BIT_65_ETC__q10, CASE_x2768_0_IF_out_fifo_internalFifos_0_first_ETC__q35, @@ -2801,16 +2801,16 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q158, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q159, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q160, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q173, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q174, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q176, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q178, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q24, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q27, @@ -2876,11 +2876,11 @@ module mkFetchStage(CLK, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q163, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q165, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q29, @@ -11268,7 +11268,7 @@ module mkFetchStage(CLK, f32d_enqReq_rl[5:0] } ; assign NOT_iTlb_to_proc_response_get_375_BIT_4_376_37_ETC___d3467 = { !iTlb$to_proc_response_get[4] && mmio$getFetchTarget == 2'd1, - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183, + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184, out_main_epoch__h116682 } ; assign NOT_out_fifo_enqueueElement_0_dummy2_1_read__9_ETC___d2167 = !out_fifo_enqueueElement_0_dummy2_1$Q_OUT || @@ -12492,9 +12492,9 @@ module mkFetchStage(CLK, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7614 = - { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 } ; + { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7623 = { SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7614, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25, @@ -12521,7 +12521,7 @@ module mkFetchStage(CLK, IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d7716, SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7644 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7927 = - { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184, + { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183, IF_SEL_ARR_out_fifo_internalFifos_0_first__526_ETC___d7723, NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d7926 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8132 = @@ -12538,9 +12538,9 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8159 = - { CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 } ; + { CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8162 = { SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8159, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, @@ -12995,6 +12995,13 @@ module mkFetchStage(CLK, 1'd1: x__h116704 = f12f2_data_1[68:5]; endcase end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: out_main_epoch__h116682 = f12f2_data_0[3:0]; + 1'd1: out_main_epoch__h116682 = f12f2_data_1[3:0]; + endcase + end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin @@ -13005,13 +13012,6 @@ module mkFetchStage(CLK, 2'd3: x__h120798 = f22f3_data_3[203]; endcase end - always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) - begin - case (f12f2_deqP) - 1'd0: out_main_epoch__h116682 = f12f2_data_0[3:0]; - 1'd1: out_main_epoch__h116682 = f12f2_data_1[3:0]; - endcase - end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin @@ -15190,22 +15190,6 @@ module mkFetchStage(CLK, 4'd13; endcase end - always@(f22f3_data_1) - begin - case (f22f3_data_1[9:6]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = - f22f3_data_1[9:6]; - 4'd11: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd10; - 4'd12: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd11; - 4'd13: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd12; - default: IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = - 4'd13; - endcase - end always@(f22f3_data_2) begin case (f22f3_data_2[9:6]) @@ -15222,6 +15206,22 @@ module mkFetchStage(CLK, 4'd13; endcase end + always@(f22f3_data_1) + begin + case (f22f3_data_1[9:6]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = + f22f3_data_1[9:6]; + 4'd11: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd10; + 4'd12: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd11; + 4'd13: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd12; + default: IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = + 4'd13; + endcase + end always@(f22f3_data_3) begin case (f22f3_data_3[9:6]) @@ -15346,21 +15346,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd7; + 4'd8; 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd7; + 4'd8; 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd7; + 4'd8; 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd7; + 4'd8; endcase end always@(f22f3_deqP or @@ -15371,21 +15371,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd8; + 4'd7; 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd8; + 4'd7; 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd8; + 4'd7; 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd8; + 4'd7; endcase end always@(f22f3_deqP or @@ -15463,31 +15463,6 @@ module mkFetchStage(CLK, 4'd4; endcase end - always@(f22f3_deqP or - IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 or - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 or - IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 or - IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd2; - 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd2; - 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd2; - 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd2; - endcase - end always@(f22f3_deqP or IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 or IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 or @@ -15521,21 +15496,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd1; + 4'd2; 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd1; + 4'd2; 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd1; + 4'd2; 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd1; + 4'd2; endcase end always@(f22f3_deqP or @@ -15563,15 +15538,29 @@ module mkFetchStage(CLK, 4'd0; endcase end - always@(f32d_deqP or f32d_data_0 or f32d_data_1) + always@(f22f3_deqP or + IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 or + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 or + IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 or + IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848) begin - case (f32d_deqP) - 1'd0: - SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = - f32d_data_0[3:0]; - 1'd1: - SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = - f32d_data_1[3:0]; + case (f22f3_deqP) + 2'd0: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == + 4'd1; + 2'd1: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == + 4'd1; + 2'd2: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == + 4'd1; + 2'd3: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == + 4'd1; endcase end always@(f22f3_deqP or @@ -15592,6 +15581,17 @@ module mkFetchStage(CLK, f22f3_data_3[202:139]; endcase end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = + f32d_data_0[3:0]; + 1'd1: + SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = + f32d_data_1[3:0]; + endcase + end always@(n__read__h122512 or instdata_data_0 or instdata_data_1) begin case (n__read__h122512) @@ -15804,6 +15804,21 @@ module mkFetchStage(CLK, 4'd9; endcase end + always@(f32d_deqP or + IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or + IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) + begin + case (f32d_deqP) + 1'd0: + SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = + IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 == + 4'd6; + 1'd1: + SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = + IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524 == + 4'd6; + endcase + end always@(f32d_deqP or IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) @@ -15834,21 +15849,6 @@ module mkFetchStage(CLK, 4'd7; endcase end - always@(f32d_deqP or - IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or - IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) - begin - case (f32d_deqP) - 1'd0: - SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = - IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 == - 4'd6; - 1'd1: - SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = - IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524 == - 4'd6; - endcase - end always@(f32d_deqP or IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) @@ -16237,75 +16237,75 @@ module mkFetchStage(CLK, 4'd13; endcase end - always@(x__h62860 or + always@(x__h72768 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62860) + case (x__h72768) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = out_fifo_internalFifos_0$D_OUT[87]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = out_fifo_internalFifos_1$D_OUT[87]; endcase end - always@(x__h62860 or + always@(x__h72768 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62860) + case (x__h72768) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = out_fifo_internalFifos_0$D_OUT[86]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = out_fifo_internalFifos_1$D_OUT[86]; endcase end - always@(x__h62860 or + always@(x__h72768 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62860) + case (x__h72768) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = out_fifo_internalFifos_0$D_OUT[85]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = out_fifo_internalFifos_1$D_OUT[85]; endcase end - always@(x__h72768 or + always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72768) + case (x__h62860) 1'd0: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = out_fifo_internalFifos_0$D_OUT[87]; 1'd1: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = out_fifo_internalFifos_1$D_OUT[87]; endcase end - always@(x__h72768 or + always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72768) + case (x__h62860) 1'd0: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = out_fifo_internalFifos_0$D_OUT[86]; 1'd1: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = out_fifo_internalFifos_1$D_OUT[86]; endcase end - always@(x__h72768 or + always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72768) + case (x__h62860) 1'd0: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = out_fifo_internalFifos_0$D_OUT[85]; 1'd1: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = out_fifo_internalFifos_1$D_OUT[85]; endcase end @@ -18409,29 +18409,29 @@ module mkFetchStage(CLK, out_fifo_internalFifos_1$D_OUT[63:32]; endcase end - always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) - begin - case (f12f2_deqP) - 1'd0: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183 = - f12f2_data_0[4]; - 1'd1: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183 = - f12f2_data_1[4]; - endcase - end always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin case (x__h62860) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183 = out_fifo_internalFifos_0$D_OUT[103:99]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183 = out_fifo_internalFifos_1$D_OUT[103:99]; endcase end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184 = + f12f2_data_0[4]; + 1'd1: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184 = + f12f2_data_1[4]; + endcase + end always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin diff --git a/src_SSITH_P3/Verilog_RTL/mkLLCache.v b/src_SSITH_P3/Verilog_RTL/mkLLCache.v index 2a4aa6a..c7ea527 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLCache.v @@ -4882,15 +4882,7 @@ module mkLLCache(CLK, assign cache_rsLdToDmaQ_clearReq_rl$EN = 1'd1 ; // register cache_rsLdToDmaQ_data_0 - assign cache_rsLdToDmaQ_data_0$D_IN = cache_rsLdToDmaQ_data_1$D_IN ; - assign cache_rsLdToDmaQ_data_0$EN = - cache_rsLdToDmaQ_enqP == 1'd0 && - NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && - cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT && - IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__70_THEN_ETC___d579 ; - - // register cache_rsLdToDmaQ_data_1 - assign cache_rsLdToDmaQ_data_1$D_IN = + assign cache_rsLdToDmaQ_data_0$D_IN = { CAN_FIRE_RL_cache_sendRsLdToDma ? cache_rsLdToDmaQ_enqReq_lat_0$wget[516:5] : cache_rsLdToDmaQ_enqReq_rl[516:5], @@ -4902,6 +4894,14 @@ module mkLLCache(CLK, CAN_FIRE_RL_cache_sendRsLdToDma ? cache_rsLdToDmaQ_enqReq_lat_0$wget[3:0] : cache_rsLdToDmaQ_enqReq_rl[3:0] } ; + assign cache_rsLdToDmaQ_data_0$EN = + cache_rsLdToDmaQ_enqP == 1'd0 && + NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && + cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT && + IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__70_THEN_ETC___d579 ; + + // register cache_rsLdToDmaQ_data_1 + assign cache_rsLdToDmaQ_data_1$D_IN = cache_rsLdToDmaQ_data_0$D_IN ; assign cache_rsLdToDmaQ_data_1$EN = cache_rsLdToDmaQ_enqP == 1'd1 && NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && @@ -5247,7 +5247,13 @@ module mkLLCache(CLK, assign cache_toMQ_clearReq_rl$EN = 1'd1 ; // register cache_toMQ_data_0 - assign cache_toMQ_data_0$D_IN = cache_toMQ_data_1$D_IN ; + assign cache_toMQ_data_0$D_IN = + { !cache_toMQ_enqReq_dummy2_2$Q_OUT || + IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_NOT_c_ETC___d828 || + (cache_toMQ_enqReq_lat_0$whas ? + cache_toMQ_enqReq_lat_0$wget[640] : + cache_toMQ_enqReq_rl[640]), + IF_cache_toMQ_enqReq_dummy2_2_read__86_AND_IF__ETC___d931 } ; assign cache_toMQ_data_0$EN = cache_toMQ_enqP == 1'd0 && NOT_cache_toMQ_clearReq_dummy2_1_read__80_81_O_ETC___d885 && @@ -5255,13 +5261,7 @@ module mkLLCache(CLK, IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_cache_ETC___d821 ; // register cache_toMQ_data_1 - assign cache_toMQ_data_1$D_IN = - { !cache_toMQ_enqReq_dummy2_2$Q_OUT || - IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_NOT_c_ETC___d828 || - (cache_toMQ_enqReq_lat_0$whas ? - cache_toMQ_enqReq_lat_0$wget[640] : - cache_toMQ_enqReq_rl[640]), - IF_cache_toMQ_enqReq_dummy2_2_read__86_AND_IF__ETC___d931 } ; + assign cache_toMQ_data_1$D_IN = cache_toMQ_data_0$D_IN ; assign cache_toMQ_data_1$EN = cache_toMQ_enqP == 1'd1 && NOT_cache_toMQ_clearReq_dummy2_1_read__80_81_O_ETC___d885 && @@ -11931,14 +11931,6 @@ module mkLLCache(CLK, 1'd1: x__h244358 = cache_rqFromCQ_data_1[3:1]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: addr__h263796 = cache_rqFromDmaQ_data_0[644:581]; - 1'd1: addr__h263796 = cache_rqFromDmaQ_data_1[644:581]; - endcase - end always@(cache_cRqRetryIndexQ_deqP or cache_cRqRetryIndexQ_data_0 or cache_cRqRetryIndexQ_data_1 or @@ -11991,6 +11983,14 @@ module mkLLCache(CLK, 1'd1: addr__h244416 = cache_rqFromCQ_data_1[72:9]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: addr__h263796 = cache_rqFromDmaQ_data_0[644:581]; + 1'd1: addr__h263796 = cache_rqFromDmaQ_data_1[644:581]; + endcase + end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) @@ -12023,16 +12023,16 @@ module mkLLCache(CLK, cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h281975 = cache_rsFromCQ_data_0[128:65]; - 1'd1: value__h281975 = cache_rsFromCQ_data_1[128:65]; + 1'd0: value__h281888 = cache_rsFromCQ_data_0[64:1]; + 1'd1: value__h281888 = cache_rsFromCQ_data_1[64:1]; endcase end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h281888 = cache_rsFromCQ_data_0[64:1]; - 1'd1: value__h281888 = cache_rsFromCQ_data_1[64:1]; + 1'd0: value__h281975 = cache_rsFromCQ_data_0[128:65]; + 1'd1: value__h281975 = cache_rsFromCQ_data_1[128:65]; endcase end always@(cache_rsFromCQ_deqP or @@ -12079,16 +12079,16 @@ module mkLLCache(CLK, cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: x__h280952 = cache_rsFromCQ_data_0[0]; - 1'd1: x__h280952 = cache_rsFromCQ_data_1[0]; + 1'd0: value__h282497 = cache_rsFromCQ_data_0[512:449]; + 1'd1: value__h282497 = cache_rsFromCQ_data_1[512:449]; endcase end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h282497 = cache_rsFromCQ_data_0[512:449]; - 1'd1: value__h282497 = cache_rsFromCQ_data_1[512:449]; + 1'd0: x__h280952 = cache_rsFromCQ_data_0[0]; + 1'd1: x__h280952 = cache_rsFromCQ_data_1[0]; endcase end always@(cache_rsFromMQ_deqP or @@ -12200,11 +12200,11 @@ module mkLLCache(CLK, begin case (cache_rqFromCQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = - !cache_rqFromCQ_data_0[4]; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = + cache_rqFromCQ_data_0[6:5] == 2'd2; 1'd1: - SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = - !cache_rqFromCQ_data_1[4]; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = + cache_rqFromCQ_data_1[6:5] == 2'd2; endcase end always@(cache_rqFromCQ_deqP or @@ -12212,11 +12212,11 @@ module mkLLCache(CLK, begin case (cache_rqFromCQ_deqP) 1'd0: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = - cache_rqFromCQ_data_0[6:5] == 2'd2; + SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = + !cache_rqFromCQ_data_0[4]; 1'd1: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = - cache_rqFromCQ_data_1[6:5] == 2'd2; + SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = + !cache_rqFromCQ_data_1[4]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12272,11 +12272,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = - !cache_rqFromDmaQ_data_0[521]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = + !cache_rqFromDmaQ_data_0[522]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = - !cache_rqFromDmaQ_data_1[521]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = + !cache_rqFromDmaQ_data_1[522]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12284,11 +12284,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = - !cache_rqFromDmaQ_data_0[522]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = + !cache_rqFromDmaQ_data_0[521]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = - !cache_rqFromDmaQ_data_1[522]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = + !cache_rqFromDmaQ_data_1[521]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12320,11 +12320,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = - !cache_rqFromDmaQ_data_0[526]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = + !cache_rqFromDmaQ_data_0[525]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = - !cache_rqFromDmaQ_data_1[526]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = + !cache_rqFromDmaQ_data_1[525]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12332,11 +12332,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = - !cache_rqFromDmaQ_data_0[525]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = + !cache_rqFromDmaQ_data_0[526]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = - !cache_rqFromDmaQ_data_1[525]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = + !cache_rqFromDmaQ_data_1[526]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12380,11 +12380,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = - !cache_rqFromDmaQ_data_0[531]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = + !cache_rqFromDmaQ_data_0[530]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = - !cache_rqFromDmaQ_data_1[531]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = + !cache_rqFromDmaQ_data_1[530]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12392,11 +12392,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = - !cache_rqFromDmaQ_data_0[530]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = + !cache_rqFromDmaQ_data_0[531]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = - !cache_rqFromDmaQ_data_1[530]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = + !cache_rqFromDmaQ_data_1[531]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12423,6 +12423,18 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[533]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = + !cache_rqFromDmaQ_data_0[535]; + 1'd1: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = + !cache_rqFromDmaQ_data_1[535]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12447,18 +12459,6 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[536]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = - !cache_rqFromDmaQ_data_0[535]; - 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = - !cache_rqFromDmaQ_data_1[535]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12524,11 +12524,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = - !cache_rqFromDmaQ_data_0[542]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = + !cache_rqFromDmaQ_data_0[543]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = - !cache_rqFromDmaQ_data_1[542]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = + !cache_rqFromDmaQ_data_1[543]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12536,11 +12536,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = - !cache_rqFromDmaQ_data_0[543]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = + !cache_rqFromDmaQ_data_0[542]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = - !cache_rqFromDmaQ_data_1[543]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = + !cache_rqFromDmaQ_data_1[542]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12560,11 +12560,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = - !cache_rqFromDmaQ_data_0[546]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = + !cache_rqFromDmaQ_data_0[545]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = - !cache_rqFromDmaQ_data_1[546]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = + !cache_rqFromDmaQ_data_1[545]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12572,11 +12572,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = - !cache_rqFromDmaQ_data_0[545]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = + !cache_rqFromDmaQ_data_0[546]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = - !cache_rqFromDmaQ_data_1[545]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = + !cache_rqFromDmaQ_data_1[546]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12692,11 +12692,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = - !cache_rqFromDmaQ_data_0[557]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = + !cache_rqFromDmaQ_data_0[556]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = - !cache_rqFromDmaQ_data_1[557]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = + !cache_rqFromDmaQ_data_1[556]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12704,11 +12704,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = - !cache_rqFromDmaQ_data_0[556]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = + !cache_rqFromDmaQ_data_0[557]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = - !cache_rqFromDmaQ_data_1[556]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = + !cache_rqFromDmaQ_data_1[557]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12764,11 +12764,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = - !cache_rqFromDmaQ_data_0[562]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = + !cache_rqFromDmaQ_data_0[563]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = - !cache_rqFromDmaQ_data_1[562]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = + !cache_rqFromDmaQ_data_1[563]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12776,11 +12776,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = - !cache_rqFromDmaQ_data_0[563]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = + !cache_rqFromDmaQ_data_0[562]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = - !cache_rqFromDmaQ_data_1[563]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = + !cache_rqFromDmaQ_data_1[562]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13040,11 +13040,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = - cache_rqFromDmaQ_data_0[324:261]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = + cache_rqFromDmaQ_data_0[388:325]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = - cache_rqFromDmaQ_data_1[324:261]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = + cache_rqFromDmaQ_data_1[388:325]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13052,11 +13052,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = - cache_rqFromDmaQ_data_0[388:325]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = + cache_rqFromDmaQ_data_0[324:261]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = - cache_rqFromDmaQ_data_1[388:325]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = + cache_rqFromDmaQ_data_1[324:261]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13148,11 +13148,11 @@ module mkLLCache(CLK, begin case (cache_rsFromMQ_deqP) 1'd0: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = - cache_rsFromMQ_data_0[452:389]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = + cache_rsFromMQ_data_0[388:325]; 1'd1: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = - cache_rsFromMQ_data_1[452:389]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = + cache_rsFromMQ_data_1[388:325]; endcase end always@(cache_rsFromMQ_deqP or @@ -13160,11 +13160,11 @@ module mkLLCache(CLK, begin case (cache_rsFromMQ_deqP) 1'd0: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = - cache_rsFromMQ_data_0[388:325]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = + cache_rsFromMQ_data_0[452:389]; 1'd1: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = - cache_rsFromMQ_data_1[388:325]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = + cache_rsFromMQ_data_1[452:389]; endcase end always@(cache_rsFromMQ_deqP or @@ -13215,74 +13215,6 @@ module mkLLCache(CLK, !cache_rsFromMQ_data_1[4]; endcase end - always@(cache_rsToCIndexQ_deqP or - cache_rsToCIndexQ_data_0 or - cache_rsToCIndexQ_data_1 or - cache_rsToCIndexQ_data_2 or - cache_rsToCIndexQ_data_3 or - cache_rsToCIndexQ_data_4 or - cache_rsToCIndexQ_data_5 or - cache_rsToCIndexQ_data_6 or - cache_rsToCIndexQ_data_7 or - cache_rsToCIndexQ_data_8 or - cache_rsToCIndexQ_data_9 or - cache_rsToCIndexQ_data_10 or - cache_rsToCIndexQ_data_11 or - cache_rsToCIndexQ_data_12 or - cache_rsToCIndexQ_data_13 or - cache_rsToCIndexQ_data_14 or cache_rsToCIndexQ_data_15) - begin - case (cache_rsToCIndexQ_deqP) - 4'd0: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_0[1:0] == 2'd1; - 4'd1: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_1[1:0] == 2'd1; - 4'd2: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_2[1:0] == 2'd1; - 4'd3: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_3[1:0] == 2'd1; - 4'd4: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_4[1:0] == 2'd1; - 4'd5: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_5[1:0] == 2'd1; - 4'd6: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_6[1:0] == 2'd1; - 4'd7: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_7[1:0] == 2'd1; - 4'd8: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_8[1:0] == 2'd1; - 4'd9: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_9[1:0] == 2'd1; - 4'd10: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_10[1:0] == 2'd1; - 4'd11: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_11[1:0] == 2'd1; - 4'd12: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_12[1:0] == 2'd1; - 4'd13: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_13[1:0] == 2'd1; - 4'd14: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_14[1:0] == 2'd1; - 4'd15: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_15[1:0] == 2'd1; - endcase - end always@(cache_rsToCIndexQ_deqP or cache_rsToCIndexQ_data_0 or cache_rsToCIndexQ_data_1 or @@ -13351,6 +13283,93 @@ module mkLLCache(CLK, cache_rsToCIndexQ_data_15[1:0] == 2'd0; endcase end + always@(cache_rsToCIndexQ_deqP or + cache_rsToCIndexQ_data_0 or + cache_rsToCIndexQ_data_1 or + cache_rsToCIndexQ_data_2 or + cache_rsToCIndexQ_data_3 or + cache_rsToCIndexQ_data_4 or + cache_rsToCIndexQ_data_5 or + cache_rsToCIndexQ_data_6 or + cache_rsToCIndexQ_data_7 or + cache_rsToCIndexQ_data_8 or + cache_rsToCIndexQ_data_9 or + cache_rsToCIndexQ_data_10 or + cache_rsToCIndexQ_data_11 or + cache_rsToCIndexQ_data_12 or + cache_rsToCIndexQ_data_13 or + cache_rsToCIndexQ_data_14 or cache_rsToCIndexQ_data_15) + begin + case (cache_rsToCIndexQ_deqP) + 4'd0: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_0[1:0] == 2'd1; + 4'd1: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_1[1:0] == 2'd1; + 4'd2: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_2[1:0] == 2'd1; + 4'd3: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_3[1:0] == 2'd1; + 4'd4: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_4[1:0] == 2'd1; + 4'd5: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_5[1:0] == 2'd1; + 4'd6: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_6[1:0] == 2'd1; + 4'd7: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_7[1:0] == 2'd1; + 4'd8: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_8[1:0] == 2'd1; + 4'd9: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_9[1:0] == 2'd1; + 4'd10: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_10[1:0] == 2'd1; + 4'd11: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_11[1:0] == 2'd1; + 4'd12: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_12[1:0] == 2'd1; + 4'd13: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_13[1:0] == 2'd1; + 4'd14: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_14[1:0] == 2'd1; + 4'd15: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_15[1:0] == 2'd1; + endcase + end + always@(cache_pipeline$unguard_first or + cache_cRqMshr$sendRqToC_searchNeedRqChild) + begin + case (cache_pipeline$unguard_first[582:581]) + 2'd0: + CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + cache_pipeline$unguard_first[580:577] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + 2'd1: + CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + !cache_pipeline$unguard_first[517] || + cache_pipeline$unguard_first[516:513] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + default: CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + !cache_pipeline$unguard_first[517] || + cache_pipeline$unguard_first[516:513] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + endcase + end always@(cache_rsToCIndexQ_deqP or cache_rsToCIndexQ_data_0 or cache_rsToCIndexQ_data_1 or @@ -13419,25 +13438,6 @@ module mkLLCache(CLK, cache_rsToCIndexQ_data_15[1:0] == 2'd2; endcase end - always@(cache_pipeline$unguard_first or - cache_cRqMshr$sendRqToC_searchNeedRqChild) - begin - case (cache_pipeline$unguard_first[582:581]) - 2'd0: - CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - cache_pipeline$unguard_first[580:577] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - 2'd1: - CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - !cache_pipeline$unguard_first[517] || - cache_pipeline$unguard_first[516:513] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - default: CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - !cache_pipeline$unguard_first[517] || - cache_pipeline$unguard_first[516:513] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - endcase - end always@(child__h356168 or cache_cRqMshr$sendRqToC_getSlot) begin case (child__h356168) @@ -15155,17 +15155,6 @@ module mkLLCache(CLK, cache_toMQ_data_1[191:128]; endcase end - always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) - begin - case (cache_toCQ_deqP) - 1'd0: - SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = - cache_toCQ_data_0[66:3]; - 1'd1: - SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = - cache_toCQ_data_1[66:3]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -15178,6 +15167,17 @@ module mkLLCache(CLK, cache_rqFromDmaQ_data_1[2:0]; endcase end + always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) + begin + case (cache_toCQ_deqP) + 1'd0: + SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = + cache_toCQ_data_0[66:3]; + 1'd1: + SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = + cache_toCQ_data_1[66:3]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin diff --git a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v index d81b40c..260231a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v @@ -1370,7 +1370,7 @@ module mkLLPipeline(CLK, MUX_m_infoRam_4_bram$a_put_1__SEL_1, MUX_m_infoRam_5_bram$a_put_1__SEL_1, MUX_m_infoRam_6_bram$a_put_1__SEL_1, - MUX_m_infoRam_7_bram$a_put_2__SEL_1, + MUX_m_infoRam_7_bram$a_put_1__SEL_1, MUX_m_infoRam_8_bram$a_put_1__SEL_1, MUX_m_infoRam_9_bram$a_put_1__SEL_1; @@ -1381,12 +1381,12 @@ module mkLLPipeline(CLK, // remaining internal signals reg [975 : 0] IF_send_r_BITS_583_TO_582_887_EQ_0_888_THEN_m__ETC___d4144; - reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3; + reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21; reg [47 : 0] y_avValue_info_tag__h200046; reg [3 : 0] CASE_send_r_BITS_583_TO_582_0_send_r_BITS_583__ETC__q2, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3858; - reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12, @@ -1398,7 +1398,7 @@ module mkLLPipeline(CLK, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20, - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21, + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8, @@ -3999,7 +3999,7 @@ module mkLLPipeline(CLK, EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd5 ; assign MUX_m_infoRam_6_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd6 ; - assign MUX_m_infoRam_7_bram$a_put_2__SEL_1 = + assign MUX_m_infoRam_7_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd7 ; assign MUX_m_infoRam_8_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd8 ; @@ -4009,11 +4009,11 @@ module mkLLPipeline(CLK, // inlined wires assign m_pipe_enq2Mat_lat_0$wget = { 1'd1, - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, IF_IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypa_ETC___d2113 } ; assign m_pipe_enq2Mat_lat_2$wget = { 1'd1, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21, IF_send_r_BITS_583_TO_582_887_EQ_0_888_THEN_m__ETC___d4165 } ; assign m_pipe_mat2Out_lat_0$wget = { deqWrite_swapRq[4], @@ -5207,12 +5207,12 @@ module mkLLPipeline(CLK, // submodule m_infoRam_7_bram assign m_infoRam_7_bram$ADDRA = - MUX_m_infoRam_7_bram$a_put_2__SEL_1 ? + MUX_m_infoRam_7_bram$a_put_1__SEL_1 ? addr__h287104[15:6] : m_initIndex ; assign m_infoRam_7_bram$ADDRB = m_infoRam_0_bram$ADDRB ; assign m_infoRam_7_bram$DIA = - MUX_m_infoRam_7_bram$a_put_2__SEL_1 ? + MUX_m_infoRam_7_bram$a_put_1__SEL_1 ? deqWrite_wrRam[571:512] : 60'd10 ; assign m_infoRam_7_bram$DIB = 60'hAAAAAAAAAAAAAAA /* unspecified value */ ; @@ -5982,7 +5982,7 @@ module mkLLPipeline(CLK, IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypass__ETC___d1611 || m_pipe_enq2Mat_rl[517], m_pipe_enq2Mat_rl[516:4], - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, m_pipe_enq2Mat_rl[1:0] } ; assign IF_IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m__ETC___d2634 = (IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 == @@ -10275,38 +10275,25 @@ module mkLLPipeline(CLK, { 2'd2, send_r[517:516] }; endcase end - always@(send_r) - begin - case (send_r[583:582]) - 2'd0: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd0, send_r[67:0] }; - 2'd1: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; - default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd2, send_r[581:518], send_r[3:0] }; - endcase - end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[3:2]) 2'd0, 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = m_pipe_enq2Mat_rl[3:2]; - default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = 2'd2; + default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = 2'd2; endcase end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[1563:1562]) 2'd0: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd0, m_pipe_enq2Mat_rl[1561:1494] }; 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = m_pipe_enq2Mat_rl[1563:1494]; - default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd2, m_pipe_enq2Mat_rl[1561:1494] }; endcase end @@ -10691,10 +10678,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3591; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3597; endcase end @@ -10704,10 +10691,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3605; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3611; endcase end @@ -10717,10 +10704,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3619; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3625; endcase end @@ -10730,10 +10717,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3633; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3639; endcase end @@ -10743,10 +10730,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3647; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3653; endcase end @@ -10756,10 +10743,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3661; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3667; endcase end @@ -10769,10 +10756,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3675; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3681; endcase end @@ -10782,10 +10769,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3689; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3695; endcase end @@ -10795,10 +10782,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3703; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3709; endcase end @@ -10808,10 +10795,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3717; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3723; endcase end @@ -10821,10 +10808,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3731; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3737; endcase end @@ -10834,10 +10821,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3745; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3751; endcase end @@ -10847,10 +10834,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3759; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3765; endcase end @@ -10860,10 +10847,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3773; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3779; endcase end @@ -10873,10 +10860,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3787; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3793; endcase end @@ -10886,14 +10873,15 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3801; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3807; endcase end always@(way__h186670 or + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 or @@ -10908,58 +10896,57 @@ module mkLLPipeline(CLK, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 or - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 or - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21) + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20) begin case (way__h186670) 4'd0: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5; 4'd1: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6; 4'd2: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7; 4'd3: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8; 4'd4: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9; 4'd5: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10; 4'd6: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11; 4'd7: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12; 4'd8: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13; 4'd9: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14; 4'd10: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15; 4'd11: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16; 4'd12: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17; 4'd13: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18; 4'd14: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19; 4'd15: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20; endcase end always@(way__h186670 or @@ -11305,6 +11292,19 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3557; endcase end + always@(send_r) + begin + case (send_r[583:582]) + 2'd0: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { 2'd0, send_r[67:0] }; + 2'd1: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; + default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { 2'd2, send_r[581:518], send_r[3:0] }; + endcase + end // handling of inlined registers diff --git a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v index c468cf5..81257fe 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v @@ -25381,75 +25381,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[66]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11078 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11079 or @@ -25519,6 +25450,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11093; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25685,75 +25685,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[64]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11115 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11116 or @@ -25823,6 +25754,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11130; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33423,89 +33423,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[13]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[13]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[13]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[13]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[13]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[13]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[13]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[13]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[13]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[13]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[13]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[13]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[13]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[13]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[13]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[13]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33589,6 +33506,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[12]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[13]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[13]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[13]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[13]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[13]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[13]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[13]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[13]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[13]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[13]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[13]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[13]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[13]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[13]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[13]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[13]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or @@ -33727,89 +33727,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[11]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[11]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[11]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[11]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[11]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[11]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[11]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[11]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[11]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[11]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[11]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[11]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[11]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[11]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[11]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[11]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33893,6 +33810,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[10]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[11]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[11]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[11]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[11]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[11]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[11]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[11]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[11]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[11]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[11]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[11]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[11]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[11]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[11]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[11]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[11]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or @@ -34031,89 +34031,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12147; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[9]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[9]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[9]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[9]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[9]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[9]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[9]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[9]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[9]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[9]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[9]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[9]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[9]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[9]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[9]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[9]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -34197,6 +34114,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[8]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[9]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[9]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[9]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[9]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[9]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[9]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[9]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[9]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[9]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[9]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[9]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[9]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[9]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[9]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[9]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[9]; + endcase + end always@(sendToM_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0850_2188_OR_NOT_ETC___d12192 or NOT_m_reqVec_1_dummy2_0_read__0855_2193_OR_NOT_ETC___d12197 or @@ -34473,6 +34473,73 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0925_AND_m_reqVe_ETC___d12286; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_15_rl[3]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -34607,73 +34674,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[3]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_15_rl[3]; - endcase - end always@(sendToM_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10950 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10951 or @@ -35088,6 +35088,75 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_dummy2_0_read__2379_AND_m_slotVec_ETC___d12419; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; + endcase + end always@(sendToM_getData_n or m_dataValidVec_0_dummy2_0_read__2569_AND_m_dat_ETC___d12574 or m_dataValidVec_1_dummy2_0_read__2575_AND_m_dat_ETC___d12580 or @@ -35157,75 +35226,6 @@ module mkLastLvCRqMshr(CLK, m_dataValidVec_15_dummy2_0_read__2659_AND_m_da_ETC___d12664; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or @@ -35296,72 +35296,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056) + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019; endcase end always@(sendRsToDmaC_getRq_n or @@ -35778,75 +35778,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11167; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11170 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11171 or @@ -35916,6 +35847,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11185; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11207 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11208 or @@ -36192,6 +36192,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11278; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11281 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11282 or @@ -36330,75 +36399,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11337 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11338 or @@ -36675,6 +36675,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11407; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11411 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11412 or @@ -36813,75 +36882,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11463; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11466 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11467 or @@ -37158,75 +37158,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11537; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or @@ -37296,6 +37227,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11577 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11578 or @@ -37779,75 +37779,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11703; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11707 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11708 or @@ -37917,6 +37848,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11722; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11744 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11745 or @@ -38193,6 +38193,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11814; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11818 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11819 or @@ -38262,6 +38331,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11833; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or @@ -38331,75 +38469,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11873 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11874 or @@ -38676,6 +38745,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11944; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11947 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11948 or @@ -38814,75 +38952,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11999; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12003 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12004 or @@ -39159,144 +39228,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092; - endcase - end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or @@ -39366,6 +39297,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12132 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12133 or @@ -39638,6 +39638,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[3]; endcase end + always@(sendRsToDmaC_getData_n or + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673 or + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680 or + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687 or + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694 or + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701 or + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708 or + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715 or + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722 or + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729 or + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736 or + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743 or + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750 or + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757 or + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764 or + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771 or + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778) + begin + case (sendRsToDmaC_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; + endcase + end always@(sendRsToDmaC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10950 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10951 or @@ -39776,75 +39845,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; endcase end - always@(sendRsToDmaC_getData_n or - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673 or - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680 or - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687 or - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694 or - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701 or - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708 or - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715 or - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722 or - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729 or - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736 or - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743 or - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750 or - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757 or - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764 or - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771 or - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778) - begin - case (sendRsToDmaC_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12782 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12784 or @@ -40121,6 +40121,75 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851 or + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853 or + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855 or + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857 or + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859 or + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861 or + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863 or + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865 or + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867 or + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869 or + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871 or + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873 or + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875 or + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877 or + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879 or + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; + endcase + end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12817 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12819 or @@ -40259,75 +40328,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12916; endcase end - always@(sendToM_getData_n or - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851 or - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853 or - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855 or - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857 or - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859 or - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861 or - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863 or - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865 or - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867 or - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869 or - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871 or - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873 or - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875 or - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877 or - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879 or - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881) - begin - case (sendToM_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12920 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12922 or @@ -40604,6 +40604,75 @@ module mkLastLvCRqMshr(CLK, m_dataValidVec_15_dummy2_0_read__2659_AND_m_da_ETC___d12664; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or @@ -40742,75 +40811,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11059 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11060 or @@ -41087,75 +41087,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11130; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11152 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11153 or @@ -41225,6 +41156,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11167; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11170 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11171 or @@ -41708,75 +41708,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11296; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or @@ -41846,6 +41777,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11337 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11338 or @@ -42122,6 +42122,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11407; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11411 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11412 or @@ -42260,75 +42329,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11463; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11466 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11467 or @@ -42605,6 +42605,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11537; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or @@ -42743,75 +42812,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11592; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11596 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11597 or @@ -43088,75 +43088,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11666; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11688 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11689 or @@ -43226,6 +43157,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11703; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11707 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11708 or @@ -43709,75 +43709,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11833; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or @@ -43847,6 +43778,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11873 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11874 or @@ -44123,6 +44123,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11944; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11947 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11948 or @@ -44261,75 +44330,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11999; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12003 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12004 or @@ -44606,6 +44606,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or @@ -44744,75 +44813,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12132 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12133 or @@ -46217,122 +46217,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[65]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[63]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[63]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[63]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[63]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[63]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[63]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[63]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[63]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[63]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[63]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[63]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[63]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[63]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[63]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[63]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[63]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46449,6 +46333,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[64]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[63]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[63]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[63]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[63]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[63]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[63]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[63]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[63]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[63]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[63]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[63]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[63]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[63]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[63]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[63]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[63]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46913,6 +46913,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[59]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[57]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[57]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[57]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[57]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[57]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[57]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[57]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[57]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[57]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[57]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[57]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[57]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[57]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[57]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[57]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[57]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47145,122 +47261,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[56]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[57]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[57]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[57]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[57]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[57]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[57]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[57]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[57]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[57]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[57]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[57]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[57]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[57]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[57]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[57]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[57]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47725,6 +47725,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[52]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[50]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[50]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[50]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[50]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[50]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[50]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[50]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[50]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[50]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[50]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[50]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[50]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[50]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[50]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[50]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[50]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47957,122 +48073,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[49]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[50]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[50]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[50]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[50]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[50]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[50]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[50]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[50]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[50]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[50]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[50]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[50]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[50]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[50]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[50]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[50]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48537,122 +48537,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[45]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[44]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[44]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[44]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[44]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[44]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[44]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[44]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[44]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[44]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[44]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[44]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[44]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[44]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[44]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[44]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[44]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48769,6 +48653,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[43]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[44]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[44]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[44]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[44]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[44]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[44]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[44]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[44]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[44]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[44]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[44]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[44]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[44]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[44]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[44]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[44]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49581,122 +49581,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[36]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[34]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[34]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[34]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[34]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[34]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[34]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[34]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[34]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[34]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[34]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[34]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[34]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[34]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[34]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[34]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[34]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49813,6 +49697,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[35]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[34]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[34]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[34]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[34]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[34]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[34]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[34]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[34]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[34]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[34]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[34]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[34]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[34]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[34]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[34]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[34]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50277,6 +50277,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[30]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[28]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[28]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[28]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[28]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[28]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[28]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[28]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[28]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[28]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[28]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[28]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[28]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[28]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[28]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[28]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[28]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50509,122 +50625,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[27]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[28]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[28]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[28]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[28]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[28]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[28]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[28]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[28]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[28]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[28]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[28]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[28]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[28]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[28]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[28]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[28]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51089,6 +51089,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[23]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[21]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[21]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[21]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[21]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[21]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[21]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[21]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[21]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[21]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[21]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[21]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[21]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[21]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[21]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[21]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[21]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51321,122 +51437,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[20]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[21]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[21]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[21]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[21]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[21]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[21]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[21]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[21]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[21]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[21]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[21]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[21]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[21]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[21]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[21]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[21]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51901,122 +51901,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[16]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[15]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[15]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[15]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[15]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[15]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[15]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[15]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[15]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[15]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[15]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[15]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[15]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[15]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[15]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[15]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[15]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52133,6 +52017,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[14]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[15]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[15]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[15]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[15]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[15]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[15]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[15]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[15]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[15]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[15]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[15]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[15]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[15]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[15]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[15]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[15]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52945,73 +52945,6 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[5]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_15_rl[3]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -53079,6 +53012,73 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_15_rl[3]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -54451,75 +54451,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12166; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12151 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12152 or @@ -54589,6 +54520,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12166; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or @@ -56065,74 +56065,6 @@ module mkLastLvCRqMshr(CLK, n__read_addr__h899290; endcase end - always@(pipelineResp_getRq_n or - n__read_addr__h995902 or - n__read_addr__h996004 or - n__read_addr__h996106 or - n__read_addr__h996208 or - n__read_addr__h996310 or - n__read_addr__h996412 or - n__read_addr__h996514 or - n__read_addr__h996616 or - n__read_addr__h996718 or - n__read_addr__h996820 or - n__read_addr__h996922 or - n__read_addr__h997024 or - n__read_addr__h997126 or - n__read_addr__h997228 or - n__read_addr__h997330 or n__read_addr__h997432) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h995902; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996004; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996106; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996208; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996310; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996412; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996514; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996616; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996718; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996820; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996922; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997024; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997126; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997228; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997330; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997432; - endcase - end always@(sendRqToC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10932 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10933 or @@ -56202,6 +56134,74 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0925_AND_m_reqVe_ETC___d10947; endcase end + always@(pipelineResp_getRq_n or + n__read_addr__h995902 or + n__read_addr__h996004 or + n__read_addr__h996106 or + n__read_addr__h996208 or + n__read_addr__h996310 or + n__read_addr__h996412 or + n__read_addr__h996514 or + n__read_addr__h996616 or + n__read_addr__h996718 or + n__read_addr__h996820 or + n__read_addr__h996922 or + n__read_addr__h997024 or + n__read_addr__h997126 or + n__read_addr__h997228 or + n__read_addr__h997330 or n__read_addr__h997432) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h995902; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996004; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996106; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996208; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996310; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996412; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996514; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996616; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996718; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996820; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996922; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997024; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997126; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997228; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997330; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997432; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -57504,107 +57504,6 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3268; endcase end - always@(transfer_getSlot_n or - m_slotVec_0_dummy2_2$Q_OUT or - IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931 or - m_slotVec_1_dummy2_2$Q_OUT or - IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018 or - m_slotVec_2_dummy2_2$Q_OUT or - IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104 or - m_slotVec_3_dummy2_2$Q_OUT or - IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190 or - m_slotVec_4_dummy2_2$Q_OUT or - IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276 or - m_slotVec_5_dummy2_2$Q_OUT or - IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362 or - m_slotVec_6_dummy2_2$Q_OUT or - IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448 or - m_slotVec_7_dummy2_2$Q_OUT or - IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534 or - m_slotVec_8_dummy2_2$Q_OUT or - IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620 or - m_slotVec_9_dummy2_2$Q_OUT or - IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706 or - m_slotVec_10_dummy2_2$Q_OUT or - IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792 or - m_slotVec_11_dummy2_2$Q_OUT or - IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878 or - m_slotVec_12_dummy2_2$Q_OUT or - IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964 or - m_slotVec_13_dummy2_2$Q_OUT or - IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050 or - m_slotVec_14_dummy2_2$Q_OUT or - IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136 or - m_slotVec_15_dummy2_2$Q_OUT or - IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222) - begin - case (transfer_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_0_dummy2_2$Q_OUT && - IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931; - 4'd1: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_1_dummy2_2$Q_OUT && - IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018; - 4'd2: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_2_dummy2_2$Q_OUT && - IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104; - 4'd3: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_3_dummy2_2$Q_OUT && - IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190; - 4'd4: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_4_dummy2_2$Q_OUT && - IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276; - 4'd5: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_5_dummy2_2$Q_OUT && - IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362; - 4'd6: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_6_dummy2_2$Q_OUT && - IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448; - 4'd7: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_7_dummy2_2$Q_OUT && - IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534; - 4'd8: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_8_dummy2_2$Q_OUT && - IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620; - 4'd9: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_9_dummy2_2$Q_OUT && - IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706; - 4'd10: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_10_dummy2_2$Q_OUT && - IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792; - 4'd11: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_11_dummy2_2$Q_OUT && - IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878; - 4'd12: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_12_dummy2_2$Q_OUT && - IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964; - 4'd13: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_13_dummy2_2$Q_OUT && - IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050; - 4'd14: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_14_dummy2_2$Q_OUT && - IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136; - 4'd15: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_15_dummy2_2$Q_OUT && - IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222; - endcase - end always@(transfer_getSlot_n or m_slotVec_0_dummy2_2$Q_OUT or IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1971 or @@ -57706,6 +57605,107 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3261; endcase end + always@(transfer_getSlot_n or + m_slotVec_0_dummy2_2$Q_OUT or + IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931 or + m_slotVec_1_dummy2_2$Q_OUT or + IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018 or + m_slotVec_2_dummy2_2$Q_OUT or + IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104 or + m_slotVec_3_dummy2_2$Q_OUT or + IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190 or + m_slotVec_4_dummy2_2$Q_OUT or + IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276 or + m_slotVec_5_dummy2_2$Q_OUT or + IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362 or + m_slotVec_6_dummy2_2$Q_OUT or + IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448 or + m_slotVec_7_dummy2_2$Q_OUT or + IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534 or + m_slotVec_8_dummy2_2$Q_OUT or + IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620 or + m_slotVec_9_dummy2_2$Q_OUT or + IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706 or + m_slotVec_10_dummy2_2$Q_OUT or + IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792 or + m_slotVec_11_dummy2_2$Q_OUT or + IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878 or + m_slotVec_12_dummy2_2$Q_OUT or + IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964 or + m_slotVec_13_dummy2_2$Q_OUT or + IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050 or + m_slotVec_14_dummy2_2$Q_OUT or + IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136 or + m_slotVec_15_dummy2_2$Q_OUT or + IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222) + begin + case (transfer_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_0_dummy2_2$Q_OUT && + IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931; + 4'd1: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_1_dummy2_2$Q_OUT && + IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018; + 4'd2: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_2_dummy2_2$Q_OUT && + IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104; + 4'd3: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_3_dummy2_2$Q_OUT && + IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190; + 4'd4: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_4_dummy2_2$Q_OUT && + IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276; + 4'd5: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_5_dummy2_2$Q_OUT && + IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362; + 4'd6: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_6_dummy2_2$Q_OUT && + IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448; + 4'd7: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_7_dummy2_2$Q_OUT && + IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534; + 4'd8: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_8_dummy2_2$Q_OUT && + IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620; + 4'd9: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_9_dummy2_2$Q_OUT && + IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706; + 4'd10: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_10_dummy2_2$Q_OUT && + IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792; + 4'd11: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_11_dummy2_2$Q_OUT && + IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878; + 4'd12: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_12_dummy2_2$Q_OUT && + IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964; + 4'd13: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_13_dummy2_2$Q_OUT && + IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050; + 4'd14: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_14_dummy2_2$Q_OUT && + IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136; + 4'd15: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_15_dummy2_2$Q_OUT && + IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222; + endcase + end always@(transfer_getSlot_n or n__read_repTag__h680626 or n__read_repTag__h680836 or diff --git a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v index 530ef3b..fbe2286 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v @@ -388,8 +388,8 @@ module mkMMIOInst(CLK, // value method getFetchTarget assign getFetchTarget = - (getFetchTarget_phyPc[63:3] >= 61'd512 && - getFetchTarget_phyPc[63:3] < 61'd1024) ? + (getFetchTarget_phyPc[63:3] >= 61'd234881024 && + getFetchTarget_phyPc[63:3] < 61'd234881536) ? 2'd1 : IF_NOT_getFetchTarget_phyPc_BITS_63_TO_3_61_UL_ETC___d276 ; assign RDY_getFetchTarget = 1'd1 ; @@ -840,7 +840,7 @@ module mkMMIOInst(CLK, // remaining internal signals assign IF_NOT_getFetchTarget_phyPc_BITS_63_TO_3_61_UL_ETC___d276 = - (getFetchTarget_phyPc[63:3] >= 61'd268435456 && + (getFetchTarget_phyPc[63:3] >= 61'd402653184 && getFetchTarget_phyPc[63:3] != toHostAddr && getFetchTarget_phyPc[63:3] != fromHostAddr) ? 2'd0 : diff --git a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v index cf79c52..aa5593b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v @@ -177,7 +177,6 @@ module mkMemLoader(CLK_portalClk, // inlined wires wire [640 : 0] memReqQ_enqReq_lat_0$wget; - wire memReqQ_enqReq_lat_0$whas; // register busy reg busy; @@ -656,6 +655,7 @@ module mkMemLoader(CLK_portalClk, wire MUX_busy$write_1__SEL_1, MUX_busy$write_1__SEL_2, MUX_expectWrData$write_1__SEL_1, + MUX_pendStCnt$write_1__SEL_2, MUX_writing$write_1__SEL_2; // remaining internal signals @@ -677,11 +677,11 @@ module mkMemLoader(CLK_portalClk, wire [31 : 0] IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187, IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41, IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11, + IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114, IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84, IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260, IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230, IF_mmio_req_wrBE_BIT_7_67_THEN_mmio_req_wrData_ETC___d993, - x__h4676, x__h6528; wire [7 : 0] IF_reqSel_70_EQ_0_77_THEN_hostWrDataQ_q_wDataO_ETC___d481, IF_reqSel_70_EQ_1_98_THEN_hostWrDataQ_q_wDataO_ETC___d500, @@ -1317,6 +1317,9 @@ module mkMemLoader(CLK_portalClk, mmio_req_wrBE_BIT_0_60_OR_mmio_req_wrBE_BIT_1__ETC___d978 ; assign MUX_expectWrData$write_1__SEL_1 = WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ; + assign MUX_pendStCnt$write_1__SEL_2 = + WILL_FIRE_RL_doStReq && + reqSel_70_EQ_7_71_OR_hostWrDataQ_q_wDataOut_wg_ETC___d930 ; assign MUX_writing$write_1__SEL_2 = WILL_FIRE_RL_doStResp && pendStCnt == 8'd1 && !expectWrData ; assign MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1 = @@ -1336,7 +1339,7 @@ module mkMemLoader(CLK_portalClk, hostWrAddrQ_q_rWrPtr_rsCounter | x__h938 : hostWrAddrQ_q_rWrPtr_rsCounter & y__h1133 ; assign MUX_hostWrDataQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrDataQ_q_rRdPtr_rsCounter[x__h4676[0]]) ? + (~hostWrDataQ_q_rRdPtr_rsCounter[IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114[0]]) ? hostWrDataQ_q_rRdPtr_rsCounter | x__h4511 : hostWrDataQ_q_rRdPtr_rsCounter & y__h4698 ; assign MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1388,9 +1391,6 @@ module mkMemLoader(CLK_portalClk, IF_reqSel_70_EQ_2_17_THEN_hostWrDataQ_q_wDataO_ETC___d721, IF_reqSel_70_EQ_1_98_THEN_hostWrDataQ_q_wDataO_ETC___d724, IF_reqSel_70_EQ_0_77_THEN_hostWrDataQ_q_wDataO_ETC___d726 } ; - assign memReqQ_enqReq_lat_0$whas = - WILL_FIRE_RL_doStReq && - reqSel_70_EQ_7_71_OR_hostWrDataQ_q_wDataOut_wg_ETC___d930 ; // register busy assign busy$D_IN = !MUX_busy$write_1__SEL_1 ; @@ -1533,7 +1533,7 @@ module mkMemLoader(CLK_portalClk, // register memReqQ_data_0 assign memReqQ_data_0$D_IN = { x_addr__h43806, - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[575:0] : memReqQ_enqReq_rl[575:0] } ; assign memReqQ_data_0$EN = @@ -1568,13 +1568,13 @@ module mkMemLoader(CLK_portalClk, // register pendStCnt always@(MUX_expectWrData$write_1__SEL_1 or - memReqQ_enqReq_lat_0$whas or + MUX_pendStCnt$write_1__SEL_2 or MUX_pendStCnt$write_1__VAL_2 or WILL_FIRE_RL_doStResp or MUX_pendStCnt$write_1__VAL_3) begin case (1'b1) // synopsys parallel_case MUX_expectWrData$write_1__SEL_1: pendStCnt$D_IN = 8'd0; - memReqQ_enqReq_lat_0$whas: + MUX_pendStCnt$write_1__SEL_2: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_2; WILL_FIRE_RL_doStResp: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_3; default: pendStCnt$D_IN = 8'b10101010 /* unspecified value */ ; @@ -1743,7 +1743,7 @@ module mkMemLoader(CLK_portalClk, // submodule memReqQ_enqReq_dummy2_0 assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign memReqQ_enqReq_dummy2_0$EN = memReqQ_enqReq_lat_0$whas ; + assign memReqQ_enqReq_dummy2_0$EN = MUX_pendStCnt$write_1__SEL_2 ; // submodule memReqQ_enqReq_dummy2_1 assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; @@ -1798,6 +1798,10 @@ module mkMemLoader(CLK_portalClk, hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10 ? 32'd1 : 32'd0 ; + assign IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 = + hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? + 32'd1 : + 32'd0 ; assign IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 = hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? 32'd1 : @@ -1811,7 +1815,7 @@ module mkMemLoader(CLK_portalClk, 32'd1 : 32'd0 ; assign IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[640] : memReqQ_enqReq_rl[640] ; assign IF_mmio_req_wrBE_BIT_7_67_THEN_mmio_req_wrData_ETC___d1000 = @@ -2045,7 +2049,7 @@ module mkMemLoader(CLK_portalClk, !memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ; assign NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366 = (!memReqQ_enqReq_dummy2_2$Q_OUT || - (memReqQ_enqReq_lat_0$whas ? + (MUX_pendStCnt$write_1__SEL_2 ? !memReqQ_enqReq_lat_0$wget[640] : !memReqQ_enqReq_rl[640])) && (memReqQ_deqReq_dummy2_2$Q_OUT && @@ -2153,11 +2157,9 @@ module mkMemLoader(CLK_portalClk, assign x__h3656 = 2'd1 << IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 ; - assign x__h4511 = 2'd1 << x__h4676 ; - assign x__h4676 = - hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? - 32'd1 : - 32'd0 ; + assign x__h4511 = + 2'd1 << + IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 ; assign x__h5470 = x_sReadBin__h4920 + 2'd1 ; assign x__h6363 = 2'd1 << x__h6528 ; assign x__h6528 = @@ -2178,7 +2180,7 @@ module mkMemLoader(CLK_portalClk, 2'd1 << IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 ; assign x_addr__h43806 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[639:576] : memReqQ_enqReq_rl[639:576] ; assign x_dReadBin__h10337 = diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index e01a625..58ecfaa 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -683,6 +683,8 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, + corew$set_htif_addrs_fromhost_addr, + corew$set_htif_addrs_tohost_addr, corew$set_verbosity_logdelay; wire [31 : 0] corew$dm_dmi_read_data, corew$dm_dmi_write_dm_word; wire [7 : 0] corew$cpu_dmem_master_arlen, @@ -737,6 +739,7 @@ module mkP3_Core(CLK, corew$EN_dm_dmi_read_data, corew$EN_dm_dmi_write, corew$EN_dm_ndm_reset_req_get_get, + corew$EN_set_htif_addrs, corew$EN_set_verbosity, corew$EN_tv_verifier_info_get_get, corew$RDY_cpu_reset_server_request_put, @@ -1228,9 +1231,12 @@ module mkP3_Core(CLK, .dm_dmi_read_addr_dm_addr(corew$dm_dmi_read_addr_dm_addr), .dm_dmi_write_dm_addr(corew$dm_dmi_write_dm_addr), .dm_dmi_write_dm_word(corew$dm_dmi_write_dm_word), + .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), + .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .EN_set_verbosity(corew$EN_set_verbosity), + .EN_set_htif_addrs(corew$EN_set_htif_addrs), .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), .EN_tv_verifier_info_get_get(corew$EN_tv_verifier_info_get_get), @@ -1239,6 +1245,7 @@ module mkP3_Core(CLK, .EN_dm_dmi_write(corew$EN_dm_dmi_write), .EN_dm_ndm_reset_req_get_get(corew$EN_dm_ndm_reset_req_get_get), .RDY_set_verbosity(), + .RDY_set_htif_addrs(), .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), @@ -1624,9 +1631,12 @@ module mkP3_Core(CLK, assign corew$dm_dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dm_dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dm_dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; + assign corew$set_htif_addrs_fromhost_addr = 64'h0 ; + assign corew$set_htif_addrs_tohost_addr = 64'h0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$EN_set_verbosity = 1'b0 ; + assign corew$EN_set_htif_addrs = 1'b0 ; assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; assign corew$EN_cpu_reset_server_response_get = corew$RDY_cpu_reset_server_response_get ; diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 1f11162..5d14a08 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1875,60 +1875,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h64898; - reg [63 : 0] v__h65518; - reg [63 : 0] v__h66335; - reg [63 : 0] v__h85916; - reg [63 : 0] v__h86536; - reg [63 : 0] v__h88783; - reg [63 : 0] v__h99220; - reg [63 : 0] v__h99988; - reg [31 : 0] v__h4974; - reg [31 : 0] v__h5140; - reg [31 : 0] v__h5418; - reg [31 : 0] v__h7457; - reg [31 : 0] v__h3250; - reg [31 : 0] v__h7758; - reg [31 : 0] v__h8249; - reg [31 : 0] v__h8412; - reg [31 : 0] v__h139957; - reg [31 : 0] v__h140124; - reg [31 : 0] v__h142227; - reg [31 : 0] v__h159573; - reg [31 : 0] v__h139339; - reg [31 : 0] v__h166268; - reg [31 : 0] v__h166776; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4968; - reg [31 : 0] v__h5134; - reg [31 : 0] v__h5412; - reg [31 : 0] v__h7451; - reg [31 : 0] v__h7752; - reg [31 : 0] v__h8243; - reg [31 : 0] v__h8406; - reg [31 : 0] v__h139333; - reg [31 : 0] v__h139951; - reg [31 : 0] v__h140118; - reg [31 : 0] v__h142221; - reg [31 : 0] v__h159567; - reg [31 : 0] v__h166262; - reg [31 : 0] v__h166770; + reg [63 : 0] v__h64914; + reg [63 : 0] v__h65534; + reg [63 : 0] v__h66351; + reg [63 : 0] v__h85932; + reg [63 : 0] v__h86552; + reg [63 : 0] v__h88799; + reg [63 : 0] v__h99236; + reg [63 : 0] v__h100004; + reg [31 : 0] v__h4988; + reg [31 : 0] v__h5154; + reg [31 : 0] v__h5432; + reg [31 : 0] v__h7471; + reg [31 : 0] v__h3264; + reg [31 : 0] v__h7772; + reg [31 : 0] v__h8263; + reg [31 : 0] v__h8426; + reg [31 : 0] v__h139973; + reg [31 : 0] v__h140140; + reg [31 : 0] v__h142243; + reg [31 : 0] v__h159589; + reg [31 : 0] v__h139355; + reg [31 : 0] v__h166284; + reg [31 : 0] v__h166792; + reg [31 : 0] v__h3258; + reg [31 : 0] v__h4982; + reg [31 : 0] v__h5148; + reg [31 : 0] v__h5426; + reg [31 : 0] v__h7465; + reg [31 : 0] v__h7766; + reg [31 : 0] v__h8257; + reg [31 : 0] v__h8420; + reg [31 : 0] v__h139349; + reg [31 : 0] v__h139967; + reg [31 : 0] v__h140134; + reg [31 : 0] v__h142237; + reg [31 : 0] v__h159583; + reg [31 : 0] v__h166278; + reg [31 : 0] v__h166786; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26, - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26, + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087, @@ -1938,34 +1938,34 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145, IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113, IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115, - data64__h153397, - ld_data__h136445, - w1__h50197, - w1__h50202, - w2__h50198, - w2__h50204, - x__h50193; + data64__h153413, + ld_data__h136461, + w1__h50213, + w1__h50218, + w2__h50214, + w2__h50220, + x__h50209; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1211; - reg [7 : 0] strb8__h153398; + reg [7 : 0] strb8__h153414; reg [5 : 0] IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_ETC___d608; - reg [2 : 0] x__h64212; - reg [1 : 0] CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14; + reg [2 : 0] x__h64228; + reg [1 : 0] CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12, + CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_IF_ETC___d1318, SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_AND__ETC___d1633, - x__h64219, - x__h85239; + x__h64235, + x__h85255; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1584; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1583; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725, - new_cline__h140260; + new_cline__h140276; wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708; wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674; @@ -1986,84 +1986,84 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_1_ETC___d781, IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1469, IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1507, - data__h31864, - failed_testnum__h168166, - mem_req_rd_addr_araddr__h139558, - mem_req_wr_addr_awaddr__h153482, - mmioPlatform_fromHostQ_data_0__h43716, - mmioPlatform_mtime__h37701, - mmioPlatform_reqData__h50789, - n__read_addr__h64080, - n__read_addr__h64165, - n__read_addr__h83001, - n__read_addr__h83080, - n__read_snd_addr__h98573, - newData__h31946, - newData__h35396, - op_result__h50805, - op_result__h51335, - op_result__h51340, - op_result__h51345, - op_result__h51350, + data__h31881, + failed_testnum__h168182, + mem_req_rd_addr_araddr__h139574, + mem_req_wr_addr_awaddr__h153498, + mmioPlatform_fromHostQ_data_0__h43732, + mmioPlatform_mtime__h37718, + mmioPlatform_reqData__h50805, + n__read_addr__h64096, + n__read_addr__h64181, + n__read_addr__h83017, + n__read_addr__h83096, + n__read_snd_addr__h98589, + newData__h31963, + newData__h35413, + op_result__h50821, + op_result__h51351, op_result__h51356, - op_result__h51363, - op_result__h51369, - result__h50248, - result__h50372, - result__h50400, - result__h50428, - result__h50456, - result__h50484, - result__h50512, - result__h50540, - result__h50568, - result__h50613, - result__h50641, - result__h50669, - result__h50697, - result__h50738, - result__h50766, - result__h50892, - result__h50919, - result__h50946, - result__h50973, - result__h51000, - result__h51027, - result__h51054, - result__h51081, - result__h51125, - result__h51152, - result__h51179, - result__h51206, - result__h51246, - result__h51273, - result__h51390, - result__h51456, - result__h51522, - result__h51588, - result__h51654, - result__h51720, - result__h51786, - result__h51848, - result__h51893, - result__h51959, - result__h52025, - result__h52083, - result__h52128, - value__h38933, - w1___1__h50307, - w2___1__h50308, - x1_avValue_data__h41372, - x1_avValue_data__h41382, - x1_avValue_data__h45993, - x1_avValue_data__h46003, - x__h32057, - x__h35487, - x__h41906, - x__h41917, - x__h43972, - x__h43983, - x__h52305; + op_result__h51361, + op_result__h51366, + op_result__h51372, + op_result__h51379, + op_result__h51385, + result__h50264, + result__h50388, + result__h50416, + result__h50444, + result__h50472, + result__h50500, + result__h50528, + result__h50556, + result__h50584, + result__h50629, + result__h50657, + result__h50685, + result__h50713, + result__h50754, + result__h50782, + result__h50908, + result__h50935, + result__h50962, + result__h50989, + result__h51016, + result__h51043, + result__h51070, + result__h51097, + result__h51141, + result__h51168, + result__h51195, + result__h51222, + result__h51262, + result__h51289, + result__h51406, + result__h51472, + result__h51538, + result__h51604, + result__h51670, + result__h51736, + result__h51802, + result__h51864, + result__h51909, + result__h51975, + result__h52041, + result__h52099, + result__h52144, + value__h38950, + w1___1__h50323, + w2___1__h50324, + x1_avValue_data__h41388, + x1_avValue_data__h41398, + x1_avValue_data__h46009, + x1_avValue_data__h46019, + x__h32074, + x__h35504, + x__h41922, + x__h41933, + x__h43988, + x__h43999, + x__h52321; wire [47 : 0] IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d675, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d748, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d865; @@ -2071,22 +2071,22 @@ module mkProc(CLK, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d666, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d743, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d860, - lower_data__h31801, + lower_data__h31818, mmioPlatform_mtime_BITS_31_TO_0__q4, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - upper_data__h31802, - v__h31657, - v__h31694, - w10197_BITS_31_TO_0__q7, - w20198_BITS_31_TO_0__q8, - x_data__h30443; + upper_data__h31819, + v__h31674, + v__h31711, + w10213_BITS_31_TO_0__q7, + w20214_BITS_31_TO_0__q8, + x_data__h30460; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389; - wire [5 : 0] x__h139593, x__h153507; + wire [5 : 0] x__h139609, x__h153523; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388; - wire [3 : 0] b__h139266, b__h3144; - wire [2 : 0] n__read_id__h64084, n__read_id__h64169; + wire [3 : 0] b__h139282, b__h3158; + wire [2 : 0] n__read_id__h64100, n__read_id__h64185; wire [1 : 0] IF_enqDst_0_lat_0_whas__263_THEN_enqDst_0_lat__ETC___d1415, IF_enqDst_0_lat_0_whas__263_THEN_enqDst_0_lat__ETC___d1426, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1560, @@ -2174,22 +2174,22 @@ module mkProc(CLK, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d452, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d474, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d524, - mmioPlatform_reqBE_BIT_0___h30068, - mmioPlatform_reqBE_BIT_4___h30028, + mmioPlatform_reqBE_BIT_0___h30085, + mmioPlatform_reqBE_BIT_4___h30045, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d593, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d702, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d775, mmioPlatform_toHostQ_enqReq_dummy2_2_read__04__ETC___d216, - n__read_child__h64085, - n__read_child__h64170, - n__read_child__h83004, - n__read_child__h83083, - n__read_snd_id__h98574, + n__read_child__h64101, + n__read_child__h64186, + n__read_child__h83020, + n__read_child__h83099, + n__read_snd_id__h98590, propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361, propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365, - x__h63898, - x__h77752, - x__h82823; + x__h63914, + x__h77768, + x__h82839; // action method hart0_server_reset_request_put assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -3362,13 +3362,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h3144 == 4'd0 ; + b__h3158 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h3144 != 4'd0 && + b__h3158 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3480,7 +3480,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h43972 == 64'd0 || + x__h43988 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3657,13 +3657,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h139266 == 4'd0 ; + b__h139282 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h139266 != 4'd0 && + b__h139282 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3671,8 +3671,8 @@ module mkProc(CLK, CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = WILL_FIRE_RL_rl_reset ; - assign WILL_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = @@ -3755,7 +3755,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30443 } ; + x_data__h30460 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 && @@ -3790,7 +3790,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__85__ETC___d1216 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31864 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31881 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3897,7 +3897,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h50193 } ; + x__h50209 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_ETC___d608, @@ -3906,52 +3906,52 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h52305, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h52321, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { 1'd1, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43972 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43988 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h43972 != 64'd0 ; + x__h43988 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41906 == 64'd0 ; + x__h41922 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898 ; + x__h63914 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15, + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823 ; + x__h82839 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26, + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732 } ; assign enqDst_0_lat_0_1$wget = - { 1'd1, n__read_snd_addr__h98573, n__read_snd_id__h98574 } ; + { 1'd1, n__read_snd_addr__h98589, n__read_snd_id__h98590 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4000,13 +4000,13 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h3144 - 4'd1 ; + b__h3158 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h3144 ; + b__h3158 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - WILL_FIRE_RL_rl_reset ? + CAN_FIRE_RL_rl_reset ? 4'd0 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = @@ -4057,13 +4057,13 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h139266 - 4'd1 ; + b__h139282 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h139266 ; + b__h139282 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - WILL_FIRE_RL_rl_reset ? + CAN_FIRE_RL_rl_reset ? 4'd0 : llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; @@ -4139,7 +4139,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h139558, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h139574, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4150,13 +4150,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h153482, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h153498, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h153397, strb8__h153398, 1'd1 } ; + { 4'd0, data64__h153413, strb8__h153414, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4168,7 +4168,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h140260 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h140276 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4305,7 +4305,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h35396 : + newData__h35413 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4314,7 +4314,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h31946 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h31963 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4744,7 +4744,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h136445, llc$dma_respLd_first[3] } ; + { ld_data__h136461, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4890,11 +4890,11 @@ module mkProc(CLK, // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = WILL_FIRE_RL_rl_reset ; + assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = WILL_FIRE_RL_rl_reset ; + assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -4935,7 +4935,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1581 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h140260, + { new_cline__h140276, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5196,54 +5196,54 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), - .amoExec_current_data(value__h38933), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h32057)); + .amoExec_current_data(value__h38950), + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h32074)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37701), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h35487)); + .amoExec_current_data(mmioPlatform_mtime__h37718), + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h35504)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h43716), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h41917)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h43732), + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h41933)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h43983)); + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h43999)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_66_BIT_ETC___d831 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h41372 } } ; + x1_avValue_data__h41388 } } ; assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_66_BIT_ETC___d879 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { IF_mmioPlatform_fromHostQ_empty_00_THEN_IF_NOT_ETC___d873, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h45993 } } ; + x1_avValue_data__h46009 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4__ETC___d690 = (IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 && !mmioPlatform_mtip_0 || @@ -5255,7 +5255,7 @@ module mkProc(CLK, (!core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) ? 67'h3AAAAAAAAAAAAAAAA : - ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd4200447) ? + ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : IF_core_0_mmioToPlatform_cRq_first__41_BITS_14_ETC___d364) ; assign IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d582 = @@ -5266,7 +5266,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 = - newData__h31946 <= mmioPlatform_mtime ; + newData__h31963 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__287_288_OR__ETC___d1322 = NOT_propDstIdx_0_dummy2_1_read__287_288_OR_IF__ETC___d1321 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5345,7 +5345,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, - x__h77752 } ; + x__h77768 } ; assign IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1584 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5368,8 +5368,8 @@ module mkProc(CLK, SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1211 ; assign IF_mmioPlatform_fromHostQ_empty_00_THEN_IF_NOT_ETC___d873 = mmioPlatform_fromHostQ_empty ? - x__h43972 == 64'd0 : - x__h41906 == 64'd0 ; + x__h43988 == 64'd0 : + x__h41922 == 64'd0 ; assign IF_mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioP_ETC___d764 = ((mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d755 && !mmioPlatform_mtip_0) ? @@ -5498,8 +5498,8 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_2_ETC___d891 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h43972 != 64'd0 : - x__h41906 != 64'd0) : + x__h43988 != 64'd0 : + x__h41922 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__54__ETC___d163 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? @@ -5745,49 +5745,49 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389 = - { CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14, + { CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732 = - { CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725, - x__h85239 } ; + x__h85255 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674 = - { CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388 = - { CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12, - x__h64212, - x__h64219 } ; - assign b__h139266 = + { CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12, + x__h64228, + x__h64235 } ; + assign b__h139282 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h3144 = + assign b__h3158 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d343 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194304 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554432 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194305 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4196352 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33556480 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4196353 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33556481 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 = core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr ; @@ -5799,24 +5799,24 @@ module mkProc(CLK, !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345) && (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] == 61'd4200447 ; + core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d539 = (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d343 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345) && (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] != 61'd4200447 && + core_0$mmioToPlatform_cRq_first[141:81] != 61'd33560575 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d545 = (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] != 61'd4200447 && + core_0$mmioToPlatform_cRq_first[141:81] != 61'd33560575 && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d359 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d552 = (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] != 61'd4200447 && + core_0$mmioToPlatform_cRq_first[141:81] != 61'd33560575 && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d359 ; assign core_0_mmioToPlatform_cRq_notEmpty__27_AND_cor_ETC___d528 = @@ -5825,22 +5825,22 @@ module mkProc(CLK, !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345) && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350 ; - assign data__h31864 = + assign data__h31881 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31657, 32'd0 } ; - assign failed_testnum__h168166 = + { v__h31674, 32'd0 } ; + assign failed_testnum__h168182 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign lower_data__h31801 = - mmioPlatform_waitLowerMSIPCRs ? v__h31694 : 32'd0 ; - assign mem_req_rd_addr_araddr__h139558 = - { llc$to_mem_toM_first[68:11], x__h139593 } ; - assign mem_req_wr_addr_awaddr__h153482 = - { llc$to_mem_toM_first[639:582], x__h153507 } ; + assign lower_data__h31818 = + mmioPlatform_waitLowerMSIPCRs ? v__h31711 : 32'd0 ; + assign mem_req_rd_addr_araddr__h139574 = + { llc$to_mem_toM_first[68:11], x__h139609 } ; + assign mem_req_wr_addr_awaddr__h153498 = + { llc$to_mem_toM_first[639:582], x__h153523 } ; assign mmioPlatform_cycle_10_ULT_99___d311 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_195_ULT_mmioPlatform__ETC___d1204 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h43716 = + assign mmioPlatform_fromHostQ_data_0__h43732 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d294 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -5851,9 +5851,9 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37701 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37718 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d755 = - mmioPlatform_mtimecmp_0 <= newData__h35396 ; + mmioPlatform_mtimecmp_0 <= newData__h35413 ; assign mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = @@ -5954,9 +5954,9 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_notEmpty && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d343 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345 ; - assign mmioPlatform_reqBE_BIT_0___h30068 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30028 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h50789 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30085 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30045 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h50805 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d593 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -5983,104 +5983,104 @@ module mkProc(CLK, !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h64080 = + assign n__read_addr__h64096 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h64165 = + assign n__read_addr__h64181 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h83001 = + assign n__read_addr__h83017 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1469 : 64'd0 ; - assign n__read_addr__h83080 = + assign n__read_addr__h83096 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1507 : 64'd0 ; - assign n__read_child__h64085 = + assign n__read_child__h64101 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h64170 = + assign n__read_child__h64186 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h83004 = + assign n__read_child__h83020 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1495 ; - assign n__read_child__h83083 = + assign n__read_child__h83099 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1533 ; - assign n__read_id__h64084 = + assign n__read_id__h64100 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h64169 = + assign n__read_id__h64185 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h98573 = + assign n__read_snd_addr__h98589 = propDstData_0_dummy2_1_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[64:1] : propDstData_0_rl_1[64:1]) : 64'd0 ; - assign n__read_snd_id__h98574 = + assign n__read_snd_id__h98590 = propDstData_0_dummy2_1_1$Q_OUT && (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[0] : propDstData_0_rl_1[0]) ; - assign newData__h31946 = + assign newData__h31963 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32057 : + x__h32074 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d683 ; - assign newData__h35396 = + assign newData__h35413 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35487 : + x__h35504 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d753 ; - assign new_cline__h140260 = + assign new_cline__h140276 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h50805 = + assign op_result__h50821 = IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 + IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ; - assign op_result__h51335 = w1__h50202 ^ w2__h50204 ; - assign op_result__h51340 = w1__h50202 & w2__h50204 ; - assign op_result__h51345 = w1__h50202 | w2__h50204 ; - assign op_result__h51350 = - (w1__h50202 < w2__h50204) ? w1__h50202 : w2__h50204 ; - assign op_result__h51356 = - (w1__h50202 <= w2__h50204) ? w2__h50204 : w1__h50202 ; - assign op_result__h51363 = + assign op_result__h51351 = w1__h50218 ^ w2__h50220 ; + assign op_result__h51356 = w1__h50218 & w2__h50220 ; + assign op_result__h51361 = w1__h50218 | w2__h50220 ; + assign op_result__h51366 = + (w1__h50218 < w2__h50220) ? w1__h50218 : w2__h50220 ; + assign op_result__h51372 = + (w1__h50218 <= w2__h50220) ? w2__h50220 : w1__h50218 ; + assign op_result__h51379 = ((IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ^ 64'h8000000000000000)) ? - w1__h50202 : - w2__h50204 ; - assign op_result__h51369 = + w1__h50218 : + w2__h50220 ; + assign op_result__h51385 = ((IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ^ 64'h8000000000000000)) ? - w2__h50204 : - w1__h50202 ; + w2__h50220 : + w1__h50218 ; assign propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6091,130 +6091,130 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h50248 = + assign result__h50264 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0] } ; - assign result__h50372 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h50400 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h50428 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h50456 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h50484 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h50512 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h50540 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h50568 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h50613 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h50641 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h50669 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h50697 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h50738 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h50766 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h50892 = + assign result__h50388 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h50416 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h50444 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h50472 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h50500 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h50528 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h50556 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h50584 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h50629 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h50657 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h50685 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h50713 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h50754 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h50782 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h50908 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h50919 = + assign result__h50935 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h50946 = + assign result__h50962 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h50973 = + assign result__h50989 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h51000 = + assign result__h51016 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h51027 = + assign result__h51043 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h51054 = + assign result__h51070 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h51081 = + assign result__h51097 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h51125 = + assign result__h51141 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h51152 = + assign result__h51168 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h51179 = + assign result__h51195 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h51206 = + assign result__h51222 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h51246 = + assign result__h51262 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h51273 = + assign result__h51289 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h51390 = + assign result__h51406 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h51456 = + assign result__h51472 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h51522 = + assign result__h51538 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h51588 = + assign result__h51604 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h51654 = + assign result__h51670 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h51720 = + assign result__h51736 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h51786 = + assign result__h51802 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h51848 = + assign result__h51864 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0] } ; - assign result__h51893 = + assign result__h51909 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h51959 = + assign result__h51975 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h52025 = + assign result__h52041 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h52083 = + assign result__h52099 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[31:0] } ; - assign result__h52128 = + assign result__h52144 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[31:0], mmioPlatform_reqData[31:0] } ; - assign upper_data__h31802 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h31657 ; - assign v__h31657 = mmioPlatform_waitUpperMSIPCRs ? v__h31694 : 32'd0 ; - assign v__h31694 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign value__h38933 = mmioPlatform_mtimecmp_0 ; - assign w10197_BITS_31_TO_0__q7 = w1__h50197[31:0] ; - assign w1___1__h50307 = { 32'd0, w1__h50197[31:0] } ; - assign w20198_BITS_31_TO_0__q8 = w2__h50198[31:0] ; - assign w2___1__h50308 = { 32'd0, w2__h50198[31:0] } ; - assign x1_avValue_data__h41372 = x1_avValue_data__h41382 ; - assign x1_avValue_data__h41382 = + assign upper_data__h31819 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h31674 ; + assign v__h31674 = mmioPlatform_waitUpperMSIPCRs ? v__h31711 : 32'd0 ; + assign v__h31711 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign value__h38950 = mmioPlatform_mtimecmp_0 ; + assign w10213_BITS_31_TO_0__q7 = w1__h50213[31:0] ; + assign w1___1__h50323 = { 32'd0, w1__h50213[31:0] } ; + assign w20214_BITS_31_TO_0__q8 = w2__h50214[31:0] ; + assign w2___1__h50324 = { 32'd0, w2__h50214[31:0] } ; + assign x1_avValue_data__h41388 = x1_avValue_data__h41398 ; + assign x1_avValue_data__h41398 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h45993 = x1_avValue_data__h46003 ; - assign x1_avValue_data__h46003 = + assign x1_avValue_data__h46009 = x1_avValue_data__h46019 ; + assign x1_avValue_data__h46019 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h139593 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h153507 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h41906 = + assign x__h139609 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h153523 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h41922 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h41917 : + x__h41933 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d870 ; - assign x__h43972 = + assign x__h43988 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h43983 : + x__h43999 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6223,123 +6223,123 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h52305 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h63898 = + assign x__h52321 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h63914 = SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_IF_ETC___d1318 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__287_288_OR_IF__ETC___d1321 ; - assign x__h77752 = + assign x__h77768 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1581 ; - assign x__h82823 = + assign x__h82839 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_AND__ETC___d1633 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__592_593_OR_I_ETC___d1636 ; - assign x_data__h30443 = { 31'd0, mmioPlatform_reqData[0] } ; + assign x_data__h30460 = { 31'd0, mmioPlatform_reqData[0] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h136445 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h136445 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h136445 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h136445 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h136445 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h136445 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h136445 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h136445 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h136461 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h136461 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h136461 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h136461 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h136461 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h136461 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h136461 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h136461 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h153397 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h153397 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h153397 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h153397 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h153397 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h153397 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h153397 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h153397 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h153413 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h153413 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h153413 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h153413 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h153413 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h153413 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h153413 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h153413 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h153398 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h153398 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h153398 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h153398 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h153398 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h153398 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h153398 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h153398 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h153414 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h153414 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h153414 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h153414 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h153414 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h153414 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h153414 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h153414 = llc$to_mem_toM_first[575:568]; endcase end always@(mmioPlatform_curReq or - result__h50613 or - result__h50641 or result__h50669 or result__h50697) + result__h50388 or + result__h50416 or + result__h50444 or + result__h50472 or + result__h50500 or + result__h50528 or result__h50556 or result__h50584) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50388; + 3'h1: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50416; + 3'h2: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50444; + 3'h3: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50472; + 3'h4: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50500; + 3'h5: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50528; + 3'h6: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50556; + 3'h7: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50584; + endcase + end + always@(mmioPlatform_curReq or + result__h50629 or + result__h50657 or result__h50685 or result__h50713) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50613; + result__h50629; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50641; + result__h50657; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50669; + result__h50685; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50697; + result__h50713; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h50372 or - result__h50400 or - result__h50428 or - result__h50456 or - result__h50484 or - result__h50512 or result__h50540 or result__h50568) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50372; - 3'h1: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50400; - 3'h2: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50428; - 3'h3: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50456; - 3'h4: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50484; - 3'h5: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50512; - 3'h6: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50540; - 3'h7: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50568; - endcase - end - always@(mmioPlatform_curReq or result__h50738 or result__h50766) + always@(mmioPlatform_curReq or result__h50754 or result__h50782) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h50738; + result__h50754; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h50766; + result__h50782; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -6351,102 +6351,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h50198 = + w2__h50214 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035; 2'b01: - w2__h50198 = + w2__h50214 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; 2'b10: - w2__h50198 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h50214 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h50198 = + w2__h50214 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 or - w2___1__h50308 or + w2___1__h50324 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055) begin case (mmioPlatform_reqSz) 2'b0: - w2__h50204 = + w2__h50220 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035; 2'b01: - w2__h50204 = + w2__h50220 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; - 2'b10: w2__h50204 = w2___1__h50308; + 2'b10: w2__h50220 = w2___1__h50324; 2'b11: - w2__h50204 = + w2__h50220 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_curReq or - result__h51125 or - result__h51152 or result__h51179 or result__h51206) + result__h51141 or + result__h51168 or result__h51195 or result__h51222) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51125; + result__h51141; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51152; + result__h51168; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51179; + result__h51195; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51206; + result__h51222; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h50892 or - result__h50919 or - result__h50946 or - result__h50973 or - result__h51000 or - result__h51027 or result__h51054 or result__h51081) + result__h50908 or + result__h50935 or + result__h50962 or + result__h50989 or + result__h51016 or + result__h51043 or result__h51070 or result__h51097) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50892; + result__h50908; 3'h1: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50919; + result__h50935; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50946; + result__h50962; 3'h3: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50973; + result__h50989; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51000; + result__h51016; 3'h5: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51027; + result__h51043; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51054; + result__h51070; 3'h7: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51081; + result__h51097; endcase end - always@(mmioPlatform_curReq or result__h51246 or result__h51273) + always@(mmioPlatform_curReq or result__h51262 or result__h51289) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h51246; + result__h51262; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h51273; + result__h51289; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -6458,41 +6458,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h50197 = + w1__h50213 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087; 2'b01: - w1__h50197 = + w1__h50213 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; 2'b10: - w1__h50197 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h50213 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h50197 = + w1__h50213 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 or - w1___1__h50307 or + w1___1__h50323 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106) begin case (mmioPlatform_reqSz) 2'b0: - w1__h50202 = + w1__h50218 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087; 2'b01: - w1__h50202 = + w1__h50218 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; - 2'b10: w1__h50202 = w1___1__h50307; + 2'b10: w1__h50218 = w1___1__h50323; 2'b11: - w1__h50202 = + w1__h50218 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 or - w10197_BITS_31_TO_0__q7 or + w10213_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106) begin case (mmioPlatform_reqSz) @@ -6504,7 +6504,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; 2'b10: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 = - { {32{w10197_BITS_31_TO_0__q7[31]}}, w10197_BITS_31_TO_0__q7 }; + { {32{w10213_BITS_31_TO_0__q7[31]}}, w10213_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; @@ -6513,7 +6513,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 or - w20198_BITS_31_TO_0__q8 or + w20214_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055) begin case (mmioPlatform_reqSz) @@ -6525,115 +6525,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; 2'b10: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 = - { {32{w20198_BITS_31_TO_0__q8[31]}}, w20198_BITS_31_TO_0__q8 }; + { {32{w20214_BITS_31_TO_0__q8[31]}}, w20214_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h51369 or - w2__h50204 or - op_result__h50805 or - op_result__h51335 or - op_result__h51340 or - op_result__h51345 or - op_result__h51363 or op_result__h51350 or op_result__h51356) + op_result__h51385 or + w2__h50220 or + op_result__h50821 or + op_result__h51351 or + op_result__h51356 or + op_result__h51361 or + op_result__h51379 or op_result__h51366 or op_result__h51372) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - w2__h50204; + w2__h50220; 4'd1: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50805; + op_result__h50821; 4'd2: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51335; + op_result__h51351; 4'd3: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51340; + op_result__h51356; 4'd4: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51345; + op_result__h51361; 4'd5: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51363; + op_result__h51379; 4'd7: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51350; + op_result__h51366; 4'd8: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51356; + op_result__h51372; default: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51369; + op_result__h51385; endcase end always@(mmioPlatform_curReq or - result__h51848 or - result__h51893 or result__h51959 or result__h52025) + result__h51864 or + result__h51909 or result__h51975 or result__h52041) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51848; + result__h51864; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51893; + result__h51909; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51959; + result__h51975; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h52025; + result__h52041; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h50248 or - result__h51390 or - result__h51456 or - result__h51522 or - result__h51588 or - result__h51654 or result__h51720 or result__h51786) + result__h50264 or + result__h51406 or + result__h51472 or + result__h51538 or + result__h51604 or + result__h51670 or result__h51736 or result__h51802) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50248; + result__h50264; 3'h1: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51390; + result__h51406; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51456; + result__h51472; 3'h3: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51522; + result__h51538; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51588; + result__h51604; 3'h5: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51654; + result__h51670; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51720; + result__h51736; 3'h7: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51786; + result__h51802; endcase end - always@(mmioPlatform_curReq or result__h52083 or result__h52128) + always@(mmioPlatform_curReq or result__h52099 or result__h52144) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h52083; + result__h52099; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h52128; + result__h52144; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -6645,15 +6645,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h50193 = + x__h50209 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169; 2'b01: - x__h50193 = + x__h50209 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178; 2'b10: - x__h50193 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h50209 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h50193 = + x__h50209 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end @@ -6737,278 +6737,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__456_THEN_propDst_ETC___d1459; endcase end - always@(x__h63898 or n__read_id__h64084 or n__read_id__h64169) + always@(x__h63914 or n__read_id__h64100 or n__read_id__h64185) begin - case (x__h63898) - 1'd0: x__h64212 = n__read_id__h64084; - 1'd1: x__h64212 = n__read_id__h64169; + case (x__h63914) + 1'd0: x__h64228 = n__read_id__h64100; + 1'd1: x__h64228 = n__read_id__h64185; endcase end - always@(x__h63898 or n__read_child__h64085 or n__read_child__h64170) + always@(x__h63914 or n__read_child__h64101 or n__read_child__h64186) begin - case (x__h63898) - 1'd0: x__h64219 = n__read_child__h64085; - 1'd1: x__h64219 = n__read_child__h64170; + case (x__h63914) + 1'd0: x__h64235 = n__read_child__h64101; + 1'd1: x__h64235 = n__read_child__h64186; endcase end - always@(x__h63898 or + always@(x__h63914 or propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361 or propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12 = + CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12 = propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361; 1'd1: - CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12 = + CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12 = propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365; endcase end - always@(x__h63898 or + always@(x__h63914 or IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1341 or IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1345) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1341; 1'd1: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1345; endcase end - always@(x__h63898 or + always@(x__h63914 or IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1351 or IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1355) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1351; 1'd1: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1355; endcase end - always@(x__h63898 or n__read_addr__h64080 or n__read_addr__h64165) + always@(x__h63914 or n__read_addr__h64096 or n__read_addr__h64181) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15 = - n__read_addr__h64080; + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15 = + n__read_addr__h64096; 1'd1: - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15 = - n__read_addr__h64165; + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15 = + n__read_addr__h64181; endcase end - always@(x__h82823 or n__read_child__h83004 or n__read_child__h83083) + always@(x__h82839 or n__read_child__h83020 or n__read_child__h83099) begin - case (x__h82823) - 1'd0: x__h85239 = n__read_child__h83004; - 1'd1: x__h85239 = n__read_child__h83083; + case (x__h82839) + 1'd0: x__h85255 = n__read_child__h83020; + 1'd1: x__h85255 = n__read_child__h83099; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h82823 or + always@(x__h82839 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1474 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1512) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1474 : 2'd0; 1'd1: - CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1512 : 2'd0; endcase end - always@(x__h82823 or + always@(x__h82839 or NOT_propDstData_1_0_dummy2_1_read__640_651_OR__ETC___d1652 or NOT_propDstData_1_1_dummy2_1_read__642_653_OR__ETC___d1654) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__640_651_OR__ETC___d1652; 1'd1: - CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__642_653_OR__ETC___d1654; endcase end - always@(x__h82823 or n__read_addr__h83001 or n__read_addr__h83080) + always@(x__h82839 or n__read_addr__h83017 or n__read_addr__h83096) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26 = - n__read_addr__h83001; + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26 = + n__read_addr__h83017; 1'd1: - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26 = - n__read_addr__h83080; + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26 = + n__read_addr__h83096; endcase end @@ -7418,13 +7418,13 @@ module mkProc(CLK, if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394) begin - v__h64898 = $time; + v__h64914 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394) - $display("%t XBar %m: deq src %d", v__h64898, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h64914, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394 && @@ -7432,30 +7432,30 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898) + x__h63914) begin - v__h65518 = $time; + v__h65534 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898) - $display("%t XBar %m: deq src %d", v__h65518, $signed(32'd1)); + x__h63914) + $display("%t XBar %m: deq src %d", v__h65534, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898 && + x__h63914 && (!propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) begin - v__h66335 = $time; + v__h66351 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) - $write("%t XBAR %m: enq dst %d ; ", v__h66335, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h66351, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) $write("CRqMsg { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) @@ -7544,13 +7544,13 @@ module mkProc(CLK, if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737) begin - v__h85916 = $time; + v__h85932 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737) - $display("%t XBar %m: deq src %d", v__h85916, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h85932, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737 && @@ -7558,30 +7558,30 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823) + x__h82839) begin - v__h86536 = $time; + v__h86552 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823) - $display("%t XBar %m: deq src %d", v__h86536, $signed(32'd1)); + x__h82839) + $display("%t XBar %m: deq src %d", v__h86552, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823 && + x__h82839 && (!propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) begin - v__h88783 = $time; + v__h88799 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) - $write("%t XBAR %m: enq dst %d ; ", v__h88783, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h88799, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) $write("CRsMsg { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) @@ -7751,12 +7751,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875) begin - v__h99220 = $time; + v__h99236 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875) - $display("%t XBar %m: deq src %d", v__h99220, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h99236, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875 && !CAN_FIRE_RL_srcPropose_4 && @@ -7765,12 +7765,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) begin - v__h99988 = $time; + v__h100004 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) - $write("%t XBAR %m: enq dst %d ; ", v__h99988, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h100004, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) $write("<"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) $write("'h%h", 1'd0); @@ -8117,7 +8117,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sendLdRespToTlb) $write("TlbLdResp { ", "data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sendLdRespToTlb) $write("'h%h", ld_data__h136445); + if (WILL_FIRE_RL_sendLdRespToTlb) $write("'h%h", ld_data__h136461); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sendLdRespToTlb) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) @@ -8183,7 +8183,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h168166); + $display("FAIL %0d", failed_testnum__h168182); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8191,14 +8191,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4974 = $stime; + v__h4988 = $stime; #0; end - v__h4968 = v__h4974 / 32'd10; + v__h4982 = v__h4988 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4968); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4982); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8257,15 +8257,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5140 = $stime; + v__h5154 = $stime; #0; end - v__h5134 = v__h5140 / 32'd10; + v__h5148 = v__h5154 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h5134); + v__h5148); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -8354,15 +8354,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5418 = $stime; + v__h5432 = $stime; #0; end - v__h5412 = v__h5418 / 32'd10; + v__h5426 = v__h5432 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h5412); + v__h5426); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8531,14 +8531,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h7457 = $stime; + v__h7471 = $stime; #0; end - v__h7451 = v__h7457 / 32'd10; + v__h7465 = v__h7471 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h7451); + $display("%0d: ERROR: CreditCounter: overflow", v__h7465); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -8691,15 +8691,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h3250 = $stime; + v__h3264 = $stime; #0; end - v__h3244 = v__h3250 / 32'd10; + v__h3258 = v__h3264 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h3244); + v__h3258); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8964,14 +8964,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h7758 = $stime; + v__h7772 = $stime; #0; end - v__h7752 = v__h7758 / 32'd10; + v__h7766 = v__h7772 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h7752); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h7766); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9008,15 +9008,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h8249 = $stime; + v__h8263 = $stime; #0; end - v__h8243 = v__h8249 / 32'd10; + v__h8257 = v__h8263 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h8243); + v__h8257); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9056,14 +9056,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h8412 = $stime; + v__h8426 = $stime; #0; end - v__h8406 = v__h8412 / 32'd10; + v__h8420 = v__h8426 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h8406); + v__h8420); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9749,8 +9749,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h31801, - upper_data__h31802); + lower_data__h31818, + upper_data__h31819); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -9817,7 +9817,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d720) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h31946, "\n"); + $write(", new mtimecmp[%d] %x", 1'd0, newData__h31963, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -9897,7 +9897,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d791) - $write(", new mtime %x", newData__h35396, ", mtimecmp "); + $write(", new mtime %x", newData__h35413, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d791) @@ -9995,7 +9995,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) - $write("'h%h", x1_avValue_data__h41382, " }"); + $write("'h%h", x1_avValue_data__h41398, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) @@ -10008,13 +10008,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43972 != 64'd0) + x__h43988 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41906 != 64'd0) + x__h41922 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -10049,7 +10049,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) - $write("'h%h", x1_avValue_data__h46003, " }"); + $write("'h%h", x1_avValue_data__h46019, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) @@ -10357,7 +10357,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", x__h52305); + $write("'h%h", x__h52321); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -10478,15 +10478,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) begin - v__h139957 = $stime; + v__h139973 = $stime; #0; end - v__h139951 = v__h139957 / 32'd10; + v__h139967 = v__h139973 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h139951, + v__h139967, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -10546,15 +10546,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h140124 = $stime; + v__h140140 = $stime; #0; end - v__h140118 = v__h140124 / 32'd10; + v__h140134 = v__h140140 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h140118); + v__h140134); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10735,16 +10735,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h142227 = $stime; + v__h142243 = $stime; #0; end - v__h142221 = v__h142227 / 32'd10; + v__h142237 = v__h142243 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h142221); + v__h142237); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11942,14 +11942,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h159573 = $stime; + v__h159589 = $stime; #0; end - v__h159567 = v__h159573 / 32'd10; + v__h159583 = v__h159589 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h159567); + $display("%0d: ERROR: CreditCounter: overflow", v__h159583); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11973,7 +11973,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", mem_req_wr_addr_awaddr__h153482); + $write("'h%h", mem_req_wr_addr_awaddr__h153498); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12069,7 +12069,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", data64__h153397); + $write("'h%h", data64__h153413); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12077,7 +12077,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", strb8__h153398); + $write("'h%h", strb8__h153414); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12103,16 +12103,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h139339 = $stime; + v__h139355 = $stime; #0; end - v__h139333 = v__h139339 / 32'd10; + v__h139349 = v__h139355 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h139333, + v__h139349, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -12200,7 +12200,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", mem_req_rd_addr_araddr__h139558); + $write("'h%h", mem_req_rd_addr_araddr__h139574); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12281,15 +12281,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) begin - v__h166268 = $stime; + v__h166284 = $stime; #0; end - v__h166262 = v__h166268 / 32'd10; + v__h166278 = v__h166284 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h166262, + v__h166278, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -12327,15 +12327,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h166776 = $stime; + v__h166792 = $stime; #0; end - v__h166770 = v__h166776 / 32'd10; + v__h166786 = v__h166792 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h166770); + v__h166786); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/src_BSV/SoC_Map.bsv b/src_SSITH_P3/src_BSV/SoC_Map.bsv index 2be7ecb..48d0fa4 100644 --- a/src_SSITH_P3/src_BSV/SoC_Map.bsv +++ b/src_SSITH_P3/src_BSV/SoC_Map.bsv @@ -27,6 +27,8 @@ package SoC_Map; // ================================================================ // Exports +export SoC_Map_Struct (..), soc_map_struct; + export SoC_Map_IFC (..), mkSoC_Map; export N_External_Interrupt_Sources; @@ -43,6 +45,36 @@ export irq_num_uart16550_0; import Fabric_Defs :: *; // Only for type Fabric_Addr +// ================================================================ +// Top-level-struct version of the SoC Map for RISCY-OOO + +typedef struct { + Bit #(64) near_mem_io_addr_base; + Bit #(64) near_mem_io_addr_size; + + Bit #(64) boot_rom_addr_base; + Bit #(64) boot_rom_addr_size; + + Bit #(64) mem0_controller_addr_base; + Bit #(64) mem0_controller_addr_size; + + Bit #(64) pc_reset_value; + } SoC_Map_Struct +deriving (FShow); + +SoC_Map_Struct soc_map_struct = +SoC_Map_Struct { + near_mem_io_addr_base: 'h_1000_0000, + + boot_rom_addr_base: 'h_7000_0000, + boot_rom_addr_size: 'h_0000_1000, + + mem0_controller_addr_base: 'h_C000_0000, + mem0_controller_addr_size: 'h_4000_0000, + + pc_reset_value: 'h_7000_0000 // = boot_rom_addr_base + }; + // ================================================================ // Interface and module for the address map diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 2646d16..306423f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -3967,7 +3967,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3, @@ -4056,7 +4056,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_4, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, @@ -4317,8 +4317,8 @@ module mkCore(CLK, reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__0001__ETC__q221, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255, CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q251, CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q252, IF_checkForException_0207_BIT_4_0208_THEN_IF_c_ETC___d20909, @@ -6023,7 +6023,7 @@ module mkCore(CLK, NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614, NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21514, NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21565, - NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708, + NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708, NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_deq_ETC___d25186, NOT_rob_deqPort_0_deq_data__3972_BITS_122_TO_1_ETC___d24474, NOT_rob_deqPort_1_deq_data__4676_BIT_25_4677_4_ETC___d24705, @@ -6526,8 +6526,8 @@ module mkCore(CLK, csrf_prv_reg_read__0001_ULE_1_4341_AND_IF_comm_ETC___d24381, csrf_prv_reg_read__0001_ULE_1___d24341, fetchStage_RDY_pipelines_0_first__9968_AND_NOT_ETC___d21158, + fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022, fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21220, - fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d21732, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d22237, fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d22360, @@ -6582,7 +6582,7 @@ module mkCore(CLK, next_deqP___1__h401670, next_deqP___1__h404895, r__h697623, - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584, + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584, regRenamingTable_RDY_rename_1_getRename__1640__ETC___d21658, regRenamingTable_rename_0_canRename__1142_AND__ETC___d21215, regRenamingTable_rename_0_canRename__1142_AND__ETC___d21469, @@ -6721,7 +6721,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23120, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23187, regRenamingTable_rename_1_canRename__1248_AND__ETC___d23472, - rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022, + rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712, specTagManager_canClaim__1140_AND_regRenamingT_ETC___d21875, specTagManager_canClaim__1140_AND_regRenamingT_ETC___d22170, v__h371968, @@ -9696,9 +9696,9 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && + l2Tlb$RDY_toChildren_rqFromC_put && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && - l2Tlb$RDY_toChildren_rqFromC_put ; + coreFix_memExe_dTlb$RDY_toParent_rqToP_first ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq @@ -9711,24 +9711,24 @@ module mkCore(CLK, // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; // rule RL_mkConnectionGetPut assign CAN_FIRE_RL_mkConnectionGetPut = - coreFix_memExe_dTlb$RDY_toParent_flush_request_get && - l2Tlb$RDY_toChildren_dTlbReqFlush_put ; + l2Tlb$RDY_toChildren_dTlbReqFlush_put && + coreFix_memExe_dTlb$RDY_toParent_flush_request_get ; assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; // rule RL_mkConnectionGetPut_1 @@ -9740,8 +9740,8 @@ module mkCore(CLK, // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = - coreFix_memExe_dTlb$RDY_toParent_flush_response_put && l2Tlb$RDY_toChildren_flushDone_get && + coreFix_memExe_dTlb$RDY_toParent_flush_response_put && fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; @@ -10083,7 +10083,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_commitTrap[133] && @@ -10133,8 +10133,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[103] && rob$deqPort_0_deq_data[18] ; @@ -10214,7 +10214,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708 && + NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708 && !commitStage_commitTrap[133] && !rob$deqPort_0_deq_data[103] && !rob$deqPort_0_deq_data[18] && @@ -10365,8 +10365,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10377,8 +10377,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10452,16 +10452,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -10472,8 +10472,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10511,8 +10511,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10609,8 +10609,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10627,8 +10627,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10650,8 +10650,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10798,8 +10798,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -10862,8 +10862,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11090,8 +11090,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11129,9 +11129,10 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + epochManager$RDY_incrementEpoch && fetchStage$RDY_pipelines_0_first && fetchStage$RDY_pipelines_0_deq && + rob$RDY_enqPort_0_enq && mmio_pRqQ_empty && epochManager$checkEpoch_0_check && fetchStage_pipelines_0_first__9971_BIT_4_0000__ETC___d20210 && @@ -11144,7 +11145,7 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022 && + fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d21037 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11495,7 +11496,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; assign MUX_rf$write_3_wr_2__SEL_5 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -11986,12 +11987,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[98:96] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : @@ -17506,24 +17507,24 @@ module mkCore(CLK, coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPredPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -17719,16 +17720,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -22473,10 +22474,10 @@ module mkCore(CLK, fetchStage$RDY_pipelines_0_first ; assign IF_fetchStage_pipelines_0_first__9971_BITS_98__ETC___d21597 = IF_fetchStage_pipelines_0_first__9971_BITS_98__ETC___d21590 || - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && (fetchStage$pipelines_0_first[98:96] != 3'd1 || specTagManager$RDY_claimSpecTag) ; assign IF_fetchStage_pipelines_0_first__9971_BIT_4_00_ETC___d21005 = @@ -22509,10 +22510,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d21677 && IF_fetchStage_RDY_pipelines_1_first__9979_AND__ETC___d21491 && (IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d21702 || - rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && + fetchStage$RDY_pipelines_1_deq && regRenamingTable$RDY_rename_1_getRename && - fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712) ; + regRenamingTable$RDY_rename_1_claimRename && + rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712) ; assign IF_fetchStage_pipelines_1_first__9980_BITS_98__ETC___d23959 = (fetchStage$pipelines_1_first[98:96] == 3'd2 && NOT_fetchStage_pipelines_0_canDeq__9969_9970_O_ETC___d22617 && @@ -24542,12 +24543,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_216_AND_rob_RDY_se_ETC___d1217 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_216_AND_rob_RDY_se_ETC___d1606 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -24619,10 +24620,10 @@ module mkCore(CLK, fetchStage$pipelines_0_first[4] || checkForException___d20207[4] || !rob$enqPort_0_canEnq ; - assign NOT_rob_deqPort_0_canDeq__4669_4670_OR_rob_RDY_ETC___d24708 = + assign NOT_rob_deqPort_0_canDeq__4669_4670_OR_regRena_ETC___d24708 = (!rob$deqPort_0_canDeq || - rob$RDY_deqPort_0_deq && - regRenamingTable$RDY_commit_0_commit) && + regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && NOT_rob_deqPort_1_deq_data__4676_BIT_25_4677_4_ETC___d24705) ; @@ -24660,7 +24661,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[122:118] == 5'd15 || rob$deqPort_1_deq_data[122:118] == 5'd19 || rob$deqPort_1_deq_data[122:118] == 5'd20 || - rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ; + regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ; assign NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21643 = !specTagManager$canClaim || NOT_regRenamingTable_rename_0_canRename__1142__ETC___d21514 || @@ -31191,7 +31192,7 @@ module mkCore(CLK, !coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2202 && !coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2205 ; assign coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2200 = - coreFix_memExe_dTlb$procResp[174:114] < 61'd268435456 ; + coreFix_memExe_dTlb$procResp[174:114] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2202 = coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ; assign coreFix_memExe_dTlb_procResp__097_BITS_174_TO__ETC___d2205 = @@ -31293,9 +31294,9 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__098_AND_coreFix_me_ETC___d24479 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && + rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__3972_BITS_122_TO_1_ETC___d24474 ; @@ -31368,6 +31369,14 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__9971_BITS_10_ETC___d21155 ; + assign fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21022 = + fetchStage$RDY_pipelines_0_first && + fetchStage$RDY_pipelines_0_deq && + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + rob$RDY_enqPort_0_enq && + (fetchStage$pipelines_0_first[98:96] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; assign fetchStage_RDY_pipelines_0_first__9968_AND_fet_ETC___d21220 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[98:96] == 3'd1 && @@ -31375,12 +31384,6 @@ module mkCore(CLK, !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__9968_AND__ETC___d21162 ; - assign fetchStage_RDY_pipelines_1_deq__9983_AND_NOT_f_ETC___d21712 = - fetchStage$RDY_pipelines_1_deq && - (!fetchStage$pipelines_0_canDeq || - NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21708) && - (fetchStage$pipelines_1_first[98:96] != 3'd1 || - specTagManager$RDY_claimSpecTag) ; assign fetchStage_pipelines_0_canDeq__9969_AND_NOT_fe_ETC___d21732 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__9971_BITS_98_ETC___d21729 && @@ -32215,7 +32218,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] % coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ; assign r__h697623 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584 = + assign regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_95_TO_9_ETC__q227 && (fetchStage$pipelines_0_first[103:99] == 5'd14 || @@ -33607,14 +33610,12 @@ module mkCore(CLK, guard__h660917 } ; assign result__h740783 = w__h740778 & y__h740812 ; assign result__h740834 = ~x__h740833 ; - assign rob_RDY_enqPort_0_enq__9995_AND_regRenamingTab_ETC___d21022 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[98:96] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign rob_RDY_enqPort_1_enq__1704_AND_NOT_fetchStage_ETC___d21712 = + rob$RDY_enqPort_1_enq && + (!fetchStage$pipelines_0_canDeq || + NOT_specTagManager_canClaim__1140_1214_OR_NOT__ETC___d21708) && + (fetchStage$pipelines_1_first[98:96] != 3'd1 || + specTagManager$RDY_claimSpecTag) ; assign rob_deqPort_0_deq_data__3972_BITS_186_TO_123_3_ETC___d24641 = rob$deqPort_0_deq_data[186:123] + 64'd4 ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q253 = @@ -39453,7 +39454,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__9971_BITS_95__ETC___d21237 or - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584 or + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1165_co_ETC___d21175 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__9971_BI_ETC___d21572 or @@ -39475,7 +39476,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[98:96] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__9971_BITS_95__ETC___d21237 || - regRenamingTable_RDY_rename_0_getRename__1015__ETC___d21584; + regRenamingTable_RDY_rename_0_getRename__1014__ETC___d21584; endcase end always@(fetchStage$pipelines_0_first or @@ -39915,39 +39916,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or - IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or - IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802 or - IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839 or - IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875 or - IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912 or - IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948 or - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or - IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 or - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) - 3'd0, 3'd2, 3'd4: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; - 3'd1: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - { IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766, - IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802, - IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839, - IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875, - IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912, - IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948, - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985, - IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 }; - 3'd3: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729; - default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839 or @@ -39992,28 +39960,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) - 3'd0, 3'd2, 3'd4: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - 3'd1: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985; - 3'd3: - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? - IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725 : - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = - coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912 or @@ -40058,6 +40004,28 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 or + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) + 3'd0, 3'd2, 3'd4: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + 3'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985; + 3'd3: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2678 ? + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2725 : + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3940 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or @@ -40120,6 +40088,39 @@ module mkCore(CLK, 3'd0; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or + IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766 or + IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802 or + IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839 or + IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875 or + IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912 or + IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948 or + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985 or + IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 or + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79]) + 3'd0, 3'd2, 3'd4: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; + 3'd1: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + { IF_coreFix_memExe_stb_deq_730_BIT_575_731_THEN_ETC___d2766, + IF_coreFix_memExe_stb_deq_730_BIT_567_767_THEN_ETC___d2802, + IF_coreFix_memExe_stb_deq_730_BIT_559_804_THEN_ETC___d2839, + IF_coreFix_memExe_stb_deq_730_BIT_551_840_THEN_ETC___d2875, + IF_coreFix_memExe_stb_deq_730_BIT_543_877_THEN_ETC___d2912, + IF_coreFix_memExe_stb_deq_730_BIT_535_913_THEN_ETC___d2948, + IF_coreFix_memExe_stb_deq_730_BIT_527_950_THEN_ETC___d2985, + IF_coreFix_memExe_stb_deq_730_BIT_519_986_THEN_ETC___d3021 }; + 3'd3: + IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2729; + default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d3025 = + coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -40394,28 +40395,6 @@ module mkCore(CLK, { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q255 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -40432,9 +40411,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q256 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q255 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q256 = 4'd15; endcase end diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index f1c4192..45250cf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -7,6 +7,7 @@ // Ports: // Name I/O size props // RDY_set_verbosity O 1 const +// RDY_set_htif_addrs O 1 const // RDY_cpu_reset_server_request_put O 1 reg // RDY_cpu_reset_server_response_get O 1 reg // cpu_imem_master_awvalid O 1 @@ -78,6 +79,8 @@ // RST_N I 1 reset // set_verbosity_verbosity I 4 // set_verbosity_logdelay I 64 unused +// set_htif_addrs_tohost_addr I 64 reg +// set_htif_addrs_fromhost_addr I 64 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 @@ -121,6 +124,7 @@ // dm_dmi_write_dm_addr I 7 // dm_dmi_write_dm_word I 32 // EN_set_verbosity I 1 +// EN_set_htif_addrs I 1 // EN_cpu_reset_server_request_put I 1 // EN_cpu_reset_server_response_get I 1 // EN_dm_dmi_read_addr I 1 @@ -159,6 +163,11 @@ module mkCoreW(CLK, EN_set_verbosity, RDY_set_verbosity, + set_htif_addrs_tohost_addr, + set_htif_addrs_fromhost_addr, + EN_set_htif_addrs, + RDY_set_htif_addrs, + EN_cpu_reset_server_request_put, RDY_cpu_reset_server_request_put, @@ -375,6 +384,12 @@ module mkCoreW(CLK, input EN_set_verbosity; output RDY_set_verbosity; + // action method set_htif_addrs + input [63 : 0] set_htif_addrs_tohost_addr; + input [63 : 0] set_htif_addrs_fromhost_addr; + input EN_set_htif_addrs; + output RDY_set_htif_addrs; + // action method cpu_reset_server_request_put input EN_cpu_reset_server_request_put; output RDY_cpu_reset_server_request_put; @@ -738,6 +753,7 @@ module mkCoreW(CLK, RDY_dm_dmi_read_data, RDY_dm_dmi_write, RDY_dm_ndm_reset_req_get_get, + RDY_set_htif_addrs, RDY_set_verbosity, RDY_tv_verifier_info_get_get, cpu_dmem_master_arlock, @@ -757,6 +773,16 @@ module mkCoreW(CLK, cpu_imem_master_wlast, cpu_imem_master_wvalid; + // register rg_fromhost_addr + reg [63 : 0] rg_fromhost_addr; + wire [63 : 0] rg_fromhost_addr$D_IN; + wire rg_fromhost_addr$EN; + + // register rg_tohost_addr + reg [63 : 0] rg_tohost_addr; + wire [63 : 0] rg_tohost_addr$D_IN; + wire rg_tohost_addr$EN; + // ports of submodule debug_module wire [76 : 0] debug_module$hart0_csr_mem_client_request_get; wire [69 : 0] debug_module$hart0_gpr_mem_client_request_get; @@ -1452,6 +1478,7 @@ module mkCoreW(CLK, CAN_FIRE_dm_dmi_read_data, CAN_FIRE_dm_dmi_write, CAN_FIRE_dm_ndm_reset_req_get_get, + CAN_FIRE_set_htif_addrs, CAN_FIRE_set_verbosity, CAN_FIRE_tv_verifier_info_get_get, WILL_FIRE_RL_ClientServerRequest, @@ -1533,17 +1560,18 @@ module mkCoreW(CLK, WILL_FIRE_dm_dmi_read_data, WILL_FIRE_dm_dmi_write, WILL_FIRE_dm_ndm_reset_req_get_get, + WILL_FIRE_set_htif_addrs, WILL_FIRE_set_verbosity, WILL_FIRE_tv_verifier_info_get_get; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h4698; - reg [31 : 0] v__h4872; - reg [31 : 0] v__h5141; - reg [31 : 0] v__h4692; - reg [31 : 0] v__h4866; - reg [31 : 0] v__h5135; + reg [31 : 0] v__h4766; + reg [31 : 0] v__h4940; + reg [31 : 0] v__h5210; + reg [31 : 0] v__h4760; + reg [31 : 0] v__h4934; + reg [31 : 0] v__h5204; // synopsys translate_on // remaining internal signals @@ -1554,6 +1582,11 @@ module mkCoreW(CLK, assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; + // action method set_htif_addrs + assign RDY_set_htif_addrs = 1'd1 ; + assign CAN_FIRE_set_htif_addrs = 1'd1 ; + assign WILL_FIRE_set_htif_addrs = EN_set_htif_addrs ; + // action method cpu_reset_server_request_put assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; @@ -2639,29 +2672,29 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; // rule RL_ClientServerResponse_1 assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_1 = CAN_FIRE_RL_ClientServerResponse_1 ; // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = - dm_gpr_tap_ifc$RDY_client_request_get && - proc$RDY_hart0_gpr_mem_server_request_put ; + proc$RDY_hart0_gpr_mem_server_request_put && + dm_gpr_tap_ifc$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = - dm_gpr_tap_ifc$RDY_client_response_put && - proc$RDY_hart0_gpr_mem_server_response_get ; + proc$RDY_hart0_gpr_mem_server_response_get && + dm_gpr_tap_ifc$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_2 = CAN_FIRE_RL_ClientServerResponse_2 ; @@ -2674,29 +2707,29 @@ module mkCoreW(CLK, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; // rule RL_ClientServerRequest_4 assign CAN_FIRE_RL_ClientServerRequest_4 = - dm_csr_tap$RDY_client_request_get && - proc$RDY_hart0_csr_mem_server_request_put ; + proc$RDY_hart0_csr_mem_server_request_put && + dm_csr_tap$RDY_client_request_get ; assign WILL_FIRE_RL_ClientServerRequest_4 = CAN_FIRE_RL_ClientServerRequest_4 ; // rule RL_ClientServerResponse_4 assign CAN_FIRE_RL_ClientServerResponse_4 = - dm_csr_tap$RDY_client_response_put && - proc$RDY_hart0_csr_mem_server_response_get ; + proc$RDY_hart0_csr_mem_server_response_get && + dm_csr_tap$RDY_client_response_put ; assign WILL_FIRE_RL_ClientServerResponse_4 = CAN_FIRE_RL_ClientServerResponse_4 ; @@ -2817,8 +2850,9 @@ module mkCoreW(CLK, // rule RL_rl_cpu_hart0_reset_from_dm_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && + plic$RDY_server_reset_request_put && debug_module$RDY_hart0_get_reset_req_get && + fabric_2x3$RDY_reset && proc$RDY_hart0_server_reset_request_put && f_reset_requestor$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = @@ -2842,6 +2876,14 @@ module mkCoreW(CLK, assign CAN_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; assign WILL_FIRE_RL_rl_relay_non_maskable_interrupt = 1'd1 ; + // register rg_fromhost_addr + assign rg_fromhost_addr$D_IN = set_htif_addrs_fromhost_addr ; + assign rg_fromhost_addr$EN = EN_set_htif_addrs ; + + // register rg_tohost_addr + assign rg_tohost_addr$D_IN = set_htif_addrs_tohost_addr ; + assign rg_tohost_addr$EN = EN_set_htif_addrs ; + // submodule debug_module assign debug_module$dmi_read_addr_dm_addr = dm_dmi_read_addr_dm_addr ; assign debug_module$dmi_write_dm_addr = dm_dmi_write_dm_addr ; @@ -3228,9 +3270,9 @@ module mkCoreW(CLK, assign proc$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign proc$set_verbosity_verbosity = set_verbosity_verbosity ; - assign proc$start_fromhostAddr = 64'd0 ; - assign proc$start_startpc = 64'h0000000000001000 ; - assign proc$start_tohostAddr = 64'h0000000080001000 ; + assign proc$start_fromhostAddr = rg_fromhost_addr ; + assign proc$start_startpc = 64'h0000000070000000 ; + assign proc$start_tohostAddr = rg_tohost_addr ; assign proc$EN_hart0_server_reset_request_put = WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; @@ -3274,6 +3316,35 @@ module mkCoreW(CLK, f_reset_reqs$EMPTY_N && f_reset_requestor$FULL_N ; + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0; + end + else + begin + if (rg_fromhost_addr$EN) + rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN; + if (rg_tohost_addr$EN) + rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA; + rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + // handling of system tasks // synopsys translate_off @@ -3283,34 +3354,34 @@ module mkCoreW(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin - v__h4698 = $stime; + v__h4766 = $stime; #0; end - v__h4692 = v__h4698 / 32'd10; + v__h4760 = v__h4766 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4692); + $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4760); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) begin - v__h4872 = $stime; + v__h4940 = $stime; #0; end - v__h4866 = v__h4872 / 32'd10; + v__h4934 = v__h4940 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h4866); + $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h4934); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) begin - v__h5141 = $stime; + v__h5210 = $stime; #0; end - v__h5135 = v__h5141 / 32'd10; + v__h5204 = v__h5210 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h5135); + v__h5204); end // synopsys translate_on endmodule // mkCoreW diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v index 19f6de0..905234d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v @@ -2694,7 +2694,7 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q75, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q16, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q168, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q187, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q49, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q51, @@ -2733,7 +2733,7 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q32, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q33, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q34; - reg CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183, + reg CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184, CASE_n__read22512_0_NOT_instdata_data_0_BIT_32_ETC__q206, CASE_n__read22512_0_NOT_instdata_data_0_BIT_65_ETC__q10, CASE_x2768_0_IF_out_fifo_internalFifos_0_first_ETC__q35, @@ -2801,16 +2801,16 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q158, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q159, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q160, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q172, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q173, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q174, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q176, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q178, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q24, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q27, @@ -2876,11 +2876,11 @@ module mkFetchStage(CLK, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q163, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q165, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q167, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q26, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q29, @@ -11268,7 +11268,7 @@ module mkFetchStage(CLK, f32d_enqReq_rl[5:0] } ; assign NOT_iTlb_to_proc_response_get_375_BIT_4_376_37_ETC___d3467 = { !iTlb$to_proc_response_get[4] && mmio$getFetchTarget == 2'd1, - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183, + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184, out_main_epoch__h116682 } ; assign NOT_out_fifo_enqueueElement_0_dummy2_1_read__9_ETC___d2167 = !out_fifo_enqueueElement_0_dummy2_1$Q_OUT || @@ -12492,9 +12492,9 @@ module mkFetchStage(CLK, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q196, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q197 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7614 = - { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 } ; + { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7623 = { SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7614, CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q25, @@ -12521,7 +12521,7 @@ module mkFetchStage(CLK, IF_SEL_ARR_IF_out_fifo_internalFifos_0_first___ETC___d7716, SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7644 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d7927 = - { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184, + { CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183, IF_SEL_ARR_out_fifo_internalFifos_0_first__526_ETC___d7723, NOT_SEL_ARR_NOT_out_fifo_internalFifos_0_first_ETC___d7926 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8132 = @@ -12538,9 +12538,9 @@ module mkFetchStage(CLK, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q201, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q202 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8159 = - { CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21, - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 } ; + { CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18, + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 } ; assign SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8162 = { SEL_ARR_out_fifo_internalFifos_0_first__526_BI_ETC___d8159, CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q23, @@ -12995,6 +12995,13 @@ module mkFetchStage(CLK, 1'd1: x__h116704 = f12f2_data_1[68:5]; endcase end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: out_main_epoch__h116682 = f12f2_data_0[3:0]; + 1'd1: out_main_epoch__h116682 = f12f2_data_1[3:0]; + endcase + end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin @@ -13005,13 +13012,6 @@ module mkFetchStage(CLK, 2'd3: x__h120798 = f22f3_data_3[203]; endcase end - always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) - begin - case (f12f2_deqP) - 1'd0: out_main_epoch__h116682 = f12f2_data_0[3:0]; - 1'd1: out_main_epoch__h116682 = f12f2_data_1[3:0]; - endcase - end always@(f22f3_deqP or f22f3_data_0 or f22f3_data_1 or f22f3_data_2 or f22f3_data_3) begin @@ -15190,22 +15190,6 @@ module mkFetchStage(CLK, 4'd13; endcase end - always@(f22f3_data_1) - begin - case (f22f3_data_1[9:6]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = - f22f3_data_1[9:6]; - 4'd11: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd10; - 4'd12: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd11; - 4'd13: - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd12; - default: IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = - 4'd13; - endcase - end always@(f22f3_data_2) begin case (f22f3_data_2[9:6]) @@ -15222,6 +15206,22 @@ module mkFetchStage(CLK, 4'd13; endcase end + always@(f22f3_data_1) + begin + case (f22f3_data_1[9:6]) + 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = + f22f3_data_1[9:6]; + 4'd11: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd10; + 4'd12: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd11; + 4'd13: + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = 4'd12; + default: IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 = + 4'd13; + endcase + end always@(f22f3_data_3) begin case (f22f3_data_3[9:6]) @@ -15346,21 +15346,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd7; + 4'd8; 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd7; + 4'd8; 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd7; + 4'd8; 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd7; + 4'd8; endcase end always@(f22f3_deqP or @@ -15371,21 +15371,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd8; + 4'd7; 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd8; + 4'd7; 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd8; + 4'd7; 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3899 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3893 = IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd8; + 4'd7; endcase end always@(f22f3_deqP or @@ -15463,31 +15463,6 @@ module mkFetchStage(CLK, 4'd4; endcase end - always@(f22f3_deqP or - IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 or - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 or - IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 or - IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848) - begin - case (f22f3_deqP) - 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd2; - 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd2; - 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd2; - 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = - IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd2; - endcase - end always@(f22f3_deqP or IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 or IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 or @@ -15521,21 +15496,21 @@ module mkFetchStage(CLK, begin case (f22f3_deqP) 2'd0: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == - 4'd1; + 4'd2; 2'd1: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == - 4'd1; + 4'd2; 2'd2: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == - 4'd1; + 4'd2; 2'd3: - SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3863 = IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == - 4'd1; + 4'd2; endcase end always@(f22f3_deqP or @@ -15563,15 +15538,29 @@ module mkFetchStage(CLK, 4'd0; endcase end - always@(f32d_deqP or f32d_data_0 or f32d_data_1) + always@(f22f3_deqP or + IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 or + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 or + IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 or + IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848) begin - case (f32d_deqP) - 1'd0: - SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = - f32d_data_0[3:0]; - 1'd1: - SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = - f32d_data_1[3:0]; + case (f22f3_deqP) + 2'd0: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_0_739_O_ETC___d3764 == + 4'd1; + 2'd1: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_1_634_BITS_9_TO_6_766_EQ_0_767_O_ETC___d3792 == + 4'd1; + 2'd2: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_2_637_BITS_9_TO_6_794_EQ_0_795_O_ETC___d3820 == + 4'd1; + 2'd3: + SEL_ARR_IF_f22f3_data_0_631_BITS_9_TO_6_738_EQ_ETC___d3857 = + IF_f22f3_data_3_640_BITS_9_TO_6_822_EQ_0_823_O_ETC___d3848 == + 4'd1; endcase end always@(f22f3_deqP or @@ -15592,6 +15581,17 @@ module mkFetchStage(CLK, f22f3_data_3[202:139]; endcase end + always@(f32d_deqP or f32d_data_0 or f32d_data_1) + begin + case (f32d_deqP) + 1'd0: + SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = + f32d_data_0[3:0]; + 1'd1: + SEL_ARR_f32d_data_0_960_BITS_3_TO_0_961_f32d_d_ETC___d3965 = + f32d_data_1[3:0]; + endcase + end always@(n__read__h122512 or instdata_data_0 or instdata_data_1) begin case (n__read__h122512) @@ -15804,6 +15804,21 @@ module mkFetchStage(CLK, 4'd9; endcase end + always@(f32d_deqP or + IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or + IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) + begin + case (f32d_deqP) + 1'd0: + SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = + IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 == + 4'd6; + 1'd1: + SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = + IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524 == + 4'd6; + endcase + end always@(f32d_deqP or IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) @@ -15834,21 +15849,6 @@ module mkFetchStage(CLK, 4'd7; endcase end - always@(f32d_deqP or - IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or - IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) - begin - case (f32d_deqP) - 1'd0: - SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = - IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 == - 4'd6; - 1'd1: - SEL_ARR_IF_f32d_data_0_960_BITS_9_TO_6_470_EQ__ETC___d4554 = - IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524 == - 4'd6; - endcase - end always@(f32d_deqP or IF_f32d_data_0_960_BITS_9_TO_6_470_EQ_0_471_OR_ETC___d4496 or IF_f32d_data_1_962_BITS_9_TO_6_498_EQ_0_499_OR_ETC___d4524) @@ -16237,75 +16237,75 @@ module mkFetchStage(CLK, 4'd13; endcase end - always@(x__h62860 or + always@(x__h72768 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62860) + case (x__h72768) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = out_fifo_internalFifos_0$D_OUT[87]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q17 = out_fifo_internalFifos_1$D_OUT[87]; endcase end - always@(x__h62860 or + always@(x__h72768 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62860) + case (x__h72768) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = out_fifo_internalFifos_0$D_OUT[86]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q18 = out_fifo_internalFifos_1$D_OUT[86]; endcase end - always@(x__h62860 or + always@(x__h72768 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h62860) + case (x__h72768) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = out_fifo_internalFifos_0$D_OUT[85]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = + CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q19 = out_fifo_internalFifos_1$D_OUT[85]; endcase end - always@(x__h72768 or + always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72768) + case (x__h62860) 1'd0: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = out_fifo_internalFifos_0$D_OUT[87]; 1'd1: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q20 = out_fifo_internalFifos_1$D_OUT[87]; endcase end - always@(x__h72768 or + always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72768) + case (x__h62860) 1'd0: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = out_fifo_internalFifos_0$D_OUT[86]; 1'd1: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q21 = out_fifo_internalFifos_1$D_OUT[86]; endcase end - always@(x__h72768 or + always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin - case (x__h72768) + case (x__h62860) 1'd0: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = out_fifo_internalFifos_0$D_OUT[85]; 1'd1: - CASE_x2768_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q22 = out_fifo_internalFifos_1$D_OUT[85]; endcase end @@ -18409,29 +18409,29 @@ module mkFetchStage(CLK, out_fifo_internalFifos_1$D_OUT[63:32]; endcase end - always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) - begin - case (f12f2_deqP) - 1'd0: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183 = - f12f2_data_0[4]; - 1'd1: - CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q183 = - f12f2_data_1[4]; - endcase - end always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin case (x__h62860) 1'd0: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183 = out_fifo_internalFifos_0$D_OUT[103:99]; 1'd1: - CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q184 = + CASE_x2860_0_out_fifo_internalFifos_0D_OUT_BI_ETC__q183 = out_fifo_internalFifos_1$D_OUT[103:99]; endcase end + always@(f12f2_deqP or f12f2_data_0 or f12f2_data_1) + begin + case (f12f2_deqP) + 1'd0: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184 = + f12f2_data_0[4]; + 1'd1: + CASE_f12f2_deqP_0_f12f2_data_0_BIT_4_1_f12f2_d_ETC__q184 = + f12f2_data_1[4]; + endcase + end always@(x__h62860 or out_fifo_internalFifos_0$D_OUT or out_fifo_internalFifos_1$D_OUT) begin diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v index 2a4aa6a..c7ea527 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v @@ -4882,15 +4882,7 @@ module mkLLCache(CLK, assign cache_rsLdToDmaQ_clearReq_rl$EN = 1'd1 ; // register cache_rsLdToDmaQ_data_0 - assign cache_rsLdToDmaQ_data_0$D_IN = cache_rsLdToDmaQ_data_1$D_IN ; - assign cache_rsLdToDmaQ_data_0$EN = - cache_rsLdToDmaQ_enqP == 1'd0 && - NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && - cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT && - IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__70_THEN_ETC___d579 ; - - // register cache_rsLdToDmaQ_data_1 - assign cache_rsLdToDmaQ_data_1$D_IN = + assign cache_rsLdToDmaQ_data_0$D_IN = { CAN_FIRE_RL_cache_sendRsLdToDma ? cache_rsLdToDmaQ_enqReq_lat_0$wget[516:5] : cache_rsLdToDmaQ_enqReq_rl[516:5], @@ -4902,6 +4894,14 @@ module mkLLCache(CLK, CAN_FIRE_RL_cache_sendRsLdToDma ? cache_rsLdToDmaQ_enqReq_lat_0$wget[3:0] : cache_rsLdToDmaQ_enqReq_rl[3:0] } ; + assign cache_rsLdToDmaQ_data_0$EN = + cache_rsLdToDmaQ_enqP == 1'd0 && + NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && + cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT && + IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__70_THEN_ETC___d579 ; + + // register cache_rsLdToDmaQ_data_1 + assign cache_rsLdToDmaQ_data_1$D_IN = cache_rsLdToDmaQ_data_0$D_IN ; assign cache_rsLdToDmaQ_data_1$EN = cache_rsLdToDmaQ_enqP == 1'd1 && NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__3_ETC___d642 && @@ -5247,7 +5247,13 @@ module mkLLCache(CLK, assign cache_toMQ_clearReq_rl$EN = 1'd1 ; // register cache_toMQ_data_0 - assign cache_toMQ_data_0$D_IN = cache_toMQ_data_1$D_IN ; + assign cache_toMQ_data_0$D_IN = + { !cache_toMQ_enqReq_dummy2_2$Q_OUT || + IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_NOT_c_ETC___d828 || + (cache_toMQ_enqReq_lat_0$whas ? + cache_toMQ_enqReq_lat_0$wget[640] : + cache_toMQ_enqReq_rl[640]), + IF_cache_toMQ_enqReq_dummy2_2_read__86_AND_IF__ETC___d931 } ; assign cache_toMQ_data_0$EN = cache_toMQ_enqP == 1'd0 && NOT_cache_toMQ_clearReq_dummy2_1_read__80_81_O_ETC___d885 && @@ -5255,13 +5261,7 @@ module mkLLCache(CLK, IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_cache_ETC___d821 ; // register cache_toMQ_data_1 - assign cache_toMQ_data_1$D_IN = - { !cache_toMQ_enqReq_dummy2_2$Q_OUT || - IF_cache_toMQ_enqReq_lat_1_whas__12_THEN_NOT_c_ETC___d828 || - (cache_toMQ_enqReq_lat_0$whas ? - cache_toMQ_enqReq_lat_0$wget[640] : - cache_toMQ_enqReq_rl[640]), - IF_cache_toMQ_enqReq_dummy2_2_read__86_AND_IF__ETC___d931 } ; + assign cache_toMQ_data_1$D_IN = cache_toMQ_data_0$D_IN ; assign cache_toMQ_data_1$EN = cache_toMQ_enqP == 1'd1 && NOT_cache_toMQ_clearReq_dummy2_1_read__80_81_O_ETC___d885 && @@ -11931,14 +11931,6 @@ module mkLLCache(CLK, 1'd1: x__h244358 = cache_rqFromCQ_data_1[3:1]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: addr__h263796 = cache_rqFromDmaQ_data_0[644:581]; - 1'd1: addr__h263796 = cache_rqFromDmaQ_data_1[644:581]; - endcase - end always@(cache_cRqRetryIndexQ_deqP or cache_cRqRetryIndexQ_data_0 or cache_cRqRetryIndexQ_data_1 or @@ -11991,6 +11983,14 @@ module mkLLCache(CLK, 1'd1: addr__h244416 = cache_rqFromCQ_data_1[72:9]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: addr__h263796 = cache_rqFromDmaQ_data_0[644:581]; + 1'd1: addr__h263796 = cache_rqFromDmaQ_data_1[644:581]; + endcase + end always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) begin case (cache_toCQ_deqP) @@ -12023,16 +12023,16 @@ module mkLLCache(CLK, cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h281975 = cache_rsFromCQ_data_0[128:65]; - 1'd1: value__h281975 = cache_rsFromCQ_data_1[128:65]; + 1'd0: value__h281888 = cache_rsFromCQ_data_0[64:1]; + 1'd1: value__h281888 = cache_rsFromCQ_data_1[64:1]; endcase end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h281888 = cache_rsFromCQ_data_0[64:1]; - 1'd1: value__h281888 = cache_rsFromCQ_data_1[64:1]; + 1'd0: value__h281975 = cache_rsFromCQ_data_0[128:65]; + 1'd1: value__h281975 = cache_rsFromCQ_data_1[128:65]; endcase end always@(cache_rsFromCQ_deqP or @@ -12079,16 +12079,16 @@ module mkLLCache(CLK, cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: x__h280952 = cache_rsFromCQ_data_0[0]; - 1'd1: x__h280952 = cache_rsFromCQ_data_1[0]; + 1'd0: value__h282497 = cache_rsFromCQ_data_0[512:449]; + 1'd1: value__h282497 = cache_rsFromCQ_data_1[512:449]; endcase end always@(cache_rsFromCQ_deqP or cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1) begin case (cache_rsFromCQ_deqP) - 1'd0: value__h282497 = cache_rsFromCQ_data_0[512:449]; - 1'd1: value__h282497 = cache_rsFromCQ_data_1[512:449]; + 1'd0: x__h280952 = cache_rsFromCQ_data_0[0]; + 1'd1: x__h280952 = cache_rsFromCQ_data_1[0]; endcase end always@(cache_rsFromMQ_deqP or @@ -12200,11 +12200,11 @@ module mkLLCache(CLK, begin case (cache_rqFromCQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = - !cache_rqFromCQ_data_0[4]; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = + cache_rqFromCQ_data_0[6:5] == 2'd2; 1'd1: - SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = - !cache_rqFromCQ_data_1[4]; + SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = + cache_rqFromCQ_data_1[6:5] == 2'd2; endcase end always@(cache_rqFromCQ_deqP or @@ -12212,11 +12212,11 @@ module mkLLCache(CLK, begin case (cache_rqFromCQ_deqP) 1'd0: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = - cache_rqFromCQ_data_0[6:5] == 2'd2; + SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = + !cache_rqFromCQ_data_0[4]; 1'd1: - SEL_ARR_cache_rqFromCQ_data_0_486_BITS_6_TO_5__ETC___d1555 = - cache_rqFromCQ_data_1[6:5] == 2'd2; + SEL_ARR_NOT_cache_rqFromCQ_data_0_486_BIT_4_50_ETC___d1564 = + !cache_rqFromCQ_data_1[4]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12272,11 +12272,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = - !cache_rqFromDmaQ_data_0[521]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = + !cache_rqFromDmaQ_data_0[522]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = - !cache_rqFromDmaQ_data_1[521]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = + !cache_rqFromDmaQ_data_1[522]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12284,11 +12284,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = - !cache_rqFromDmaQ_data_0[522]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = + !cache_rqFromDmaQ_data_0[521]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1617 = - !cache_rqFromDmaQ_data_1[522]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1610 = + !cache_rqFromDmaQ_data_1[521]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12320,11 +12320,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = - !cache_rqFromDmaQ_data_0[526]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = + !cache_rqFromDmaQ_data_0[525]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = - !cache_rqFromDmaQ_data_1[526]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = + !cache_rqFromDmaQ_data_1[525]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12332,11 +12332,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = - !cache_rqFromDmaQ_data_0[525]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = + !cache_rqFromDmaQ_data_0[526]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1638 = - !cache_rqFromDmaQ_data_1[525]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_52_ETC___d1645 = + !cache_rqFromDmaQ_data_1[526]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12380,11 +12380,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = - !cache_rqFromDmaQ_data_0[531]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = + !cache_rqFromDmaQ_data_0[530]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = - !cache_rqFromDmaQ_data_1[531]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = + !cache_rqFromDmaQ_data_1[530]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12392,11 +12392,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = - !cache_rqFromDmaQ_data_0[530]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = + !cache_rqFromDmaQ_data_0[531]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1673 = - !cache_rqFromDmaQ_data_1[530]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1680 = + !cache_rqFromDmaQ_data_1[531]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12423,6 +12423,18 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[533]; endcase end + always@(cache_rqFromDmaQ_deqP or + cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) + begin + case (cache_rqFromDmaQ_deqP) + 1'd0: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = + !cache_rqFromDmaQ_data_0[535]; + 1'd1: + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = + !cache_rqFromDmaQ_data_1[535]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12447,18 +12459,6 @@ module mkLLCache(CLK, !cache_rqFromDmaQ_data_1[536]; endcase end - always@(cache_rqFromDmaQ_deqP or - cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) - begin - case (cache_rqFromDmaQ_deqP) - 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = - !cache_rqFromDmaQ_data_0[535]; - 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_53_ETC___d1708 = - !cache_rqFromDmaQ_data_1[535]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -12524,11 +12524,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = - !cache_rqFromDmaQ_data_0[542]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = + !cache_rqFromDmaQ_data_0[543]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = - !cache_rqFromDmaQ_data_1[542]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = + !cache_rqFromDmaQ_data_1[543]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12536,11 +12536,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = - !cache_rqFromDmaQ_data_0[543]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = + !cache_rqFromDmaQ_data_0[542]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1764 = - !cache_rqFromDmaQ_data_1[543]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1757 = + !cache_rqFromDmaQ_data_1[542]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12560,11 +12560,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = - !cache_rqFromDmaQ_data_0[546]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = + !cache_rqFromDmaQ_data_0[545]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = - !cache_rqFromDmaQ_data_1[546]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = + !cache_rqFromDmaQ_data_1[545]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12572,11 +12572,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = - !cache_rqFromDmaQ_data_0[545]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = + !cache_rqFromDmaQ_data_0[546]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1778 = - !cache_rqFromDmaQ_data_1[545]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_54_ETC___d1785 = + !cache_rqFromDmaQ_data_1[546]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12692,11 +12692,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = - !cache_rqFromDmaQ_data_0[557]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = + !cache_rqFromDmaQ_data_0[556]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = - !cache_rqFromDmaQ_data_1[557]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = + !cache_rqFromDmaQ_data_1[556]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12704,11 +12704,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = - !cache_rqFromDmaQ_data_0[556]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = + !cache_rqFromDmaQ_data_0[557]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1855 = - !cache_rqFromDmaQ_data_1[556]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_55_ETC___d1862 = + !cache_rqFromDmaQ_data_1[557]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12764,11 +12764,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = - !cache_rqFromDmaQ_data_0[562]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = + !cache_rqFromDmaQ_data_0[563]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = - !cache_rqFromDmaQ_data_1[562]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = + !cache_rqFromDmaQ_data_1[563]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -12776,11 +12776,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = - !cache_rqFromDmaQ_data_0[563]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = + !cache_rqFromDmaQ_data_0[562]; 1'd1: - SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1904 = - !cache_rqFromDmaQ_data_1[563]; + SEL_ARR_NOT_cache_rqFromDmaQ_data_0_571_BIT_56_ETC___d1897 = + !cache_rqFromDmaQ_data_1[562]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13040,11 +13040,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = - cache_rqFromDmaQ_data_0[324:261]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = + cache_rqFromDmaQ_data_0[388:325]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = - cache_rqFromDmaQ_data_1[324:261]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = + cache_rqFromDmaQ_data_1[388:325]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13052,11 +13052,11 @@ module mkLLCache(CLK, begin case (cache_rqFromDmaQ_deqP) 1'd0: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = - cache_rqFromDmaQ_data_0[388:325]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = + cache_rqFromDmaQ_data_0[324:261]; 1'd1: - SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_388_T_ETC___d2345 = - cache_rqFromDmaQ_data_1[388:325]; + SEL_ARR_cache_rqFromDmaQ_data_0_571_BITS_324_T_ETC___d2349 = + cache_rqFromDmaQ_data_1[324:261]; endcase end always@(cache_rqFromDmaQ_deqP or @@ -13148,11 +13148,11 @@ module mkLLCache(CLK, begin case (cache_rsFromMQ_deqP) 1'd0: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = - cache_rsFromMQ_data_0[452:389]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = + cache_rsFromMQ_data_0[388:325]; 1'd1: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = - cache_rsFromMQ_data_1[452:389]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = + cache_rsFromMQ_data_1[388:325]; endcase end always@(cache_rsFromMQ_deqP or @@ -13160,11 +13160,11 @@ module mkLLCache(CLK, begin case (cache_rsFromMQ_deqP) 1'd0: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = - cache_rsFromMQ_data_0[388:325]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = + cache_rsFromMQ_data_0[452:389]; 1'd1: - SEL_ARR_cache_rsFromMQ_data_0_460_BITS_388_TO__ETC___d2489 = - cache_rsFromMQ_data_1[388:325]; + SEL_ARR_cache_rsFromMQ_data_0_460_BITS_452_TO__ETC___d2484 = + cache_rsFromMQ_data_1[452:389]; endcase end always@(cache_rsFromMQ_deqP or @@ -13215,74 +13215,6 @@ module mkLLCache(CLK, !cache_rsFromMQ_data_1[4]; endcase end - always@(cache_rsToCIndexQ_deqP or - cache_rsToCIndexQ_data_0 or - cache_rsToCIndexQ_data_1 or - cache_rsToCIndexQ_data_2 or - cache_rsToCIndexQ_data_3 or - cache_rsToCIndexQ_data_4 or - cache_rsToCIndexQ_data_5 or - cache_rsToCIndexQ_data_6 or - cache_rsToCIndexQ_data_7 or - cache_rsToCIndexQ_data_8 or - cache_rsToCIndexQ_data_9 or - cache_rsToCIndexQ_data_10 or - cache_rsToCIndexQ_data_11 or - cache_rsToCIndexQ_data_12 or - cache_rsToCIndexQ_data_13 or - cache_rsToCIndexQ_data_14 or cache_rsToCIndexQ_data_15) - begin - case (cache_rsToCIndexQ_deqP) - 4'd0: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_0[1:0] == 2'd1; - 4'd1: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_1[1:0] == 2'd1; - 4'd2: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_2[1:0] == 2'd1; - 4'd3: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_3[1:0] == 2'd1; - 4'd4: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_4[1:0] == 2'd1; - 4'd5: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_5[1:0] == 2'd1; - 4'd6: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_6[1:0] == 2'd1; - 4'd7: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_7[1:0] == 2'd1; - 4'd8: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_8[1:0] == 2'd1; - 4'd9: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_9[1:0] == 2'd1; - 4'd10: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_10[1:0] == 2'd1; - 4'd11: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_11[1:0] == 2'd1; - 4'd12: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_12[1:0] == 2'd1; - 4'd13: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_13[1:0] == 2'd1; - 4'd14: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_14[1:0] == 2'd1; - 4'd15: - SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = - cache_rsToCIndexQ_data_15[1:0] == 2'd1; - endcase - end always@(cache_rsToCIndexQ_deqP or cache_rsToCIndexQ_data_0 or cache_rsToCIndexQ_data_1 or @@ -13351,6 +13283,93 @@ module mkLLCache(CLK, cache_rsToCIndexQ_data_15[1:0] == 2'd0; endcase end + always@(cache_rsToCIndexQ_deqP or + cache_rsToCIndexQ_data_0 or + cache_rsToCIndexQ_data_1 or + cache_rsToCIndexQ_data_2 or + cache_rsToCIndexQ_data_3 or + cache_rsToCIndexQ_data_4 or + cache_rsToCIndexQ_data_5 or + cache_rsToCIndexQ_data_6 or + cache_rsToCIndexQ_data_7 or + cache_rsToCIndexQ_data_8 or + cache_rsToCIndexQ_data_9 or + cache_rsToCIndexQ_data_10 or + cache_rsToCIndexQ_data_11 or + cache_rsToCIndexQ_data_12 or + cache_rsToCIndexQ_data_13 or + cache_rsToCIndexQ_data_14 or cache_rsToCIndexQ_data_15) + begin + case (cache_rsToCIndexQ_deqP) + 4'd0: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_0[1:0] == 2'd1; + 4'd1: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_1[1:0] == 2'd1; + 4'd2: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_2[1:0] == 2'd1; + 4'd3: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_3[1:0] == 2'd1; + 4'd4: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_4[1:0] == 2'd1; + 4'd5: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_5[1:0] == 2'd1; + 4'd6: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_6[1:0] == 2'd1; + 4'd7: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_7[1:0] == 2'd1; + 4'd8: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_8[1:0] == 2'd1; + 4'd9: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_9[1:0] == 2'd1; + 4'd10: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_10[1:0] == 2'd1; + 4'd11: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_11[1:0] == 2'd1; + 4'd12: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_12[1:0] == 2'd1; + 4'd13: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_13[1:0] == 2'd1; + 4'd14: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_14[1:0] == 2'd1; + 4'd15: + SEL_ARR_cache_rsToCIndexQ_data_0_653_BITS_1_TO_ETC___d3909 = + cache_rsToCIndexQ_data_15[1:0] == 2'd1; + endcase + end + always@(cache_pipeline$unguard_first or + cache_cRqMshr$sendRqToC_searchNeedRqChild) + begin + case (cache_pipeline$unguard_first[582:581]) + 2'd0: + CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + cache_pipeline$unguard_first[580:577] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + 2'd1: + CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + !cache_pipeline$unguard_first[517] || + cache_pipeline$unguard_first[516:513] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + default: CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = + !cache_pipeline$unguard_first[517] || + cache_pipeline$unguard_first[516:513] != + cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; + endcase + end always@(cache_rsToCIndexQ_deqP or cache_rsToCIndexQ_data_0 or cache_rsToCIndexQ_data_1 or @@ -13419,25 +13438,6 @@ module mkLLCache(CLK, cache_rsToCIndexQ_data_15[1:0] == 2'd2; endcase end - always@(cache_pipeline$unguard_first or - cache_cRqMshr$sendRqToC_searchNeedRqChild) - begin - case (cache_pipeline$unguard_first[582:581]) - 2'd0: - CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - cache_pipeline$unguard_first[580:577] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - 2'd1: - CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - !cache_pipeline$unguard_first[517] || - cache_pipeline$unguard_first[516:513] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - default: CASE_cache_pipelineunguard_first_BITS_582_TO__ETC__q6 = - !cache_pipeline$unguard_first[517] || - cache_pipeline$unguard_first[516:513] != - cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0]; - endcase - end always@(child__h356168 or cache_cRqMshr$sendRqToC_getSlot) begin case (child__h356168) @@ -15155,17 +15155,6 @@ module mkLLCache(CLK, cache_toMQ_data_1[191:128]; endcase end - always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) - begin - case (cache_toCQ_deqP) - 1'd0: - SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = - cache_toCQ_data_0[66:3]; - 1'd1: - SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = - cache_toCQ_data_1[66:3]; - endcase - end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin @@ -15178,6 +15167,17 @@ module mkLLCache(CLK, cache_rqFromDmaQ_data_1[2:0]; endcase end + always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1) + begin + case (cache_toCQ_deqP) + 1'd0: + SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = + cache_toCQ_data_0[66:3]; + 1'd1: + SEL_ARR_cache_toCQ_data_0_715_BITS_66_TO_3_724_ETC___d9727 = + cache_toCQ_data_1[66:3]; + endcase + end always@(cache_rqFromDmaQ_deqP or cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1) begin diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v index d81b40c..260231a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v @@ -1370,7 +1370,7 @@ module mkLLPipeline(CLK, MUX_m_infoRam_4_bram$a_put_1__SEL_1, MUX_m_infoRam_5_bram$a_put_1__SEL_1, MUX_m_infoRam_6_bram$a_put_1__SEL_1, - MUX_m_infoRam_7_bram$a_put_2__SEL_1, + MUX_m_infoRam_7_bram$a_put_1__SEL_1, MUX_m_infoRam_8_bram$a_put_1__SEL_1, MUX_m_infoRam_9_bram$a_put_1__SEL_1; @@ -1381,12 +1381,12 @@ module mkLLPipeline(CLK, // remaining internal signals reg [975 : 0] IF_send_r_BITS_583_TO_582_887_EQ_0_888_THEN_m__ETC___d4144; - reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3; + reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21; reg [47 : 0] y_avValue_info_tag__h200046; reg [3 : 0] CASE_send_r_BITS_583_TO_582_0_send_r_BITS_583__ETC__q2, SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3858; - reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12, @@ -1398,7 +1398,7 @@ module mkLLPipeline(CLK, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20, - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21, + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8, @@ -3999,7 +3999,7 @@ module mkLLPipeline(CLK, EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd5 ; assign MUX_m_infoRam_6_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd6 ; - assign MUX_m_infoRam_7_bram$a_put_2__SEL_1 = + assign MUX_m_infoRam_7_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd7 ; assign MUX_m_infoRam_8_bram$a_put_1__SEL_1 = EN_deqWrite && m_pipe_mat2Out_rl[577:574] == 4'd8 ; @@ -4009,11 +4009,11 @@ module mkLLPipeline(CLK, // inlined wires assign m_pipe_enq2Mat_lat_0$wget = { 1'd1, - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5, + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4, IF_IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypa_ETC___d2113 } ; assign m_pipe_enq2Mat_lat_2$wget = { 1'd1, - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3, + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21, IF_send_r_BITS_583_TO_582_887_EQ_0_888_THEN_m__ETC___d4165 } ; assign m_pipe_mat2Out_lat_0$wget = { deqWrite_swapRq[4], @@ -5207,12 +5207,12 @@ module mkLLPipeline(CLK, // submodule m_infoRam_7_bram assign m_infoRam_7_bram$ADDRA = - MUX_m_infoRam_7_bram$a_put_2__SEL_1 ? + MUX_m_infoRam_7_bram$a_put_1__SEL_1 ? addr__h287104[15:6] : m_initIndex ; assign m_infoRam_7_bram$ADDRB = m_infoRam_0_bram$ADDRB ; assign m_infoRam_7_bram$DIA = - MUX_m_infoRam_7_bram$a_put_2__SEL_1 ? + MUX_m_infoRam_7_bram$a_put_1__SEL_1 ? deqWrite_wrRam[571:512] : 60'd10 ; assign m_infoRam_7_bram$DIB = 60'hAAAAAAAAAAAAAAA /* unspecified value */ ; @@ -5982,7 +5982,7 @@ module mkLLPipeline(CLK, IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypass__ETC___d1611 || m_pipe_enq2Mat_rl[517], m_pipe_enq2Mat_rl[516:4], - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4, + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3, m_pipe_enq2Mat_rl[1:0] } ; assign IF_IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m__ETC___d2634 = (IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 == @@ -10275,38 +10275,25 @@ module mkLLPipeline(CLK, { 2'd2, send_r[517:516] }; endcase end - always@(send_r) - begin - case (send_r[583:582]) - 2'd0: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd0, send_r[67:0] }; - 2'd1: - CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; - default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 = - { 2'd2, send_r[581:518], send_r[3:0] }; - endcase - end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[3:2]) 2'd0, 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = + CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = m_pipe_enq2Mat_rl[3:2]; - default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = 2'd2; + default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = 2'd2; endcase end always@(m_pipe_enq2Mat_rl) begin case (m_pipe_enq2Mat_rl[1563:1562]) 2'd0: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd0, m_pipe_enq2Mat_rl[1561:1494] }; 2'd1: - CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = m_pipe_enq2Mat_rl[1563:1494]; - default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 = + default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 = { 2'd2, m_pipe_enq2Mat_rl[1561:1494] }; endcase end @@ -10691,10 +10678,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3591; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3597; endcase end @@ -10704,10 +10691,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3605; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3611; endcase end @@ -10717,10 +10704,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3619; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3625; endcase end @@ -10730,10 +10717,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3633; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3639; endcase end @@ -10743,10 +10730,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3647; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3653; endcase end @@ -10756,10 +10743,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3661; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3667; endcase end @@ -10769,10 +10756,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3675; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3681; endcase end @@ -10782,10 +10769,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3689; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3695; endcase end @@ -10795,10 +10782,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3703; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3709; endcase end @@ -10808,10 +10795,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3717; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3723; endcase end @@ -10821,10 +10808,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3731; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3737; endcase end @@ -10834,10 +10821,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3745; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3751; endcase end @@ -10847,10 +10834,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3759; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3765; endcase end @@ -10860,10 +10847,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3773; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3779; endcase end @@ -10873,10 +10860,10 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3787; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3793; endcase end @@ -10886,14 +10873,15 @@ module mkLLPipeline(CLK, begin case (value__h163680) 1'd0: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3801; 1'd1: - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21 = + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 = IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3807; endcase end always@(way__h186670 or + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8 or @@ -10908,58 +10896,57 @@ module mkLLPipeline(CLK, CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18 or CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19 or - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20 or - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21) + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20) begin case (way__h186670) 4'd0: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q5; 4'd1: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q6; 4'd2: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q7; 4'd3: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q8; 4'd4: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q9; 4'd5: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q10; 4'd6: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q11; 4'd7: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q12; 4'd8: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q13; 4'd9: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q14; 4'd10: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q15; 4'd11: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q16; 4'd12: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q17; 4'd13: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q18; 4'd14: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q19; 4'd15: SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3811 = - CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q21; + CASE_value63680_0_IF_m_pipe_enq2Mat_dummy2_1_r_ETC__q20; endcase end always@(way__h186670 or @@ -11305,6 +11292,19 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3557; endcase end + always@(send_r) + begin + case (send_r[583:582]) + 2'd0: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { 2'd0, send_r[67:0] }; + 2'd1: + CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { send_r[583:582], 3'h2, send_r[579:516], send_r[0] }; + default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 = + { 2'd2, send_r[581:518], send_r[3:0] }; + endcase + end // handling of inlined registers diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v index c468cf5..81257fe 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v @@ -25381,75 +25381,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[66]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11078 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11079 or @@ -25519,6 +25450,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11093; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11096; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11097; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11098; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11099; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11100; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11101; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11102; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11103; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11104; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11105; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11106; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11107; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11108; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11109; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11110; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11113 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11111; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -25685,75 +25685,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[64]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; - endcase - end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11115 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11116 or @@ -25823,6 +25754,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11130; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d11150 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; + endcase + end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33423,89 +33423,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[13]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[13]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[13]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[13]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[13]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[13]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[13]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[13]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[13]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[13]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[13]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[13]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[13]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[13]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[13]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[13]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33589,6 +33506,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[12]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[13]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[13]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[13]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[13]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[13]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[13]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[13]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[13]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[13]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[13]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[13]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[13]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[13]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[13]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[13]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9774 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[13]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or @@ -33727,89 +33727,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[11]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[11]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[11]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[11]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[11]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[11]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[11]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[11]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[11]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[11]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[11]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[11]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[11]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[11]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[11]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[11]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -33893,6 +33810,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[10]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[11]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[11]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[11]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[11]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[11]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[11]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[11]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[11]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[11]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[11]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[11]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[11]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[11]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[11]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[11]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d9971 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[11]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or @@ -34031,89 +34031,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12147; endcase end - always@(transfer_getRq_n or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (transfer_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[9]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[9]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[9]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[9]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[9]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[9]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[9]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[9]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[9]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[9]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[9]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[9]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[9]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[9]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[9]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = - m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[9]; - endcase - end always@(transfer_getRq_n or m_reqVec_0_dummy2_2$Q_OUT or m_reqVec_0_rl or @@ -34197,6 +34114,89 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[8]; endcase end + always@(transfer_getRq_n or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (transfer_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_0_dummy2_2$Q_OUT && m_reqVec_0_rl[9]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_1_dummy2_2$Q_OUT && m_reqVec_1_rl[9]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_2_dummy2_2$Q_OUT && m_reqVec_2_rl[9]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_3_dummy2_2$Q_OUT && m_reqVec_3_rl[9]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_4_dummy2_2$Q_OUT && m_reqVec_4_rl[9]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_5_dummy2_2$Q_OUT && m_reqVec_5_rl[9]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_6_dummy2_2$Q_OUT && m_reqVec_6_rl[9]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_7_dummy2_2$Q_OUT && m_reqVec_7_rl[9]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_8_dummy2_2$Q_OUT && m_reqVec_8_rl[9]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_9_dummy2_2$Q_OUT && m_reqVec_9_rl[9]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_10_dummy2_2$Q_OUT && m_reqVec_10_rl[9]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_11_dummy2_2$Q_OUT && m_reqVec_11_rl[9]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_12_dummy2_2$Q_OUT && m_reqVec_12_rl[9]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_13_dummy2_2$Q_OUT && m_reqVec_13_rl[9]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_14_dummy2_2$Q_OUT && m_reqVec_14_rl[9]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_2_read__055_AND_IF_m_ETC___d10168 = + m_reqVec_15_dummy2_2$Q_OUT && m_reqVec_15_rl[9]; + endcase + end always@(sendToM_getRq_n or NOT_m_reqVec_0_dummy2_0_read__0850_2188_OR_NOT_ETC___d12192 or NOT_m_reqVec_1_dummy2_0_read__0855_2193_OR_NOT_ETC___d12197 or @@ -34473,6 +34473,73 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0925_AND_m_reqVe_ETC___d12286; endcase end + always@(sendToM_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (sendToM_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = + m_reqVec_15_rl[3]; + endcase + end always@(sendToM_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -34607,73 +34674,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[3]; endcase end - always@(sendToM_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (sendToM_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_m_reqVec_0_rl_0_BIT_3_0524_m_reqVec_1__ETC___d12294 = - m_reqVec_15_rl[3]; - endcase - end always@(sendToM_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10950 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10951 or @@ -35088,6 +35088,75 @@ module mkLastLvCRqMshr(CLK, m_slotVec_15_dummy2_0_read__2379_AND_m_slotVec_ETC___d12419; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; + endcase + end always@(sendToM_getData_n or m_dataValidVec_0_dummy2_0_read__2569_AND_m_dat_ETC___d12574 or m_dataValidVec_1_dummy2_0_read__2575_AND_m_dat_ETC___d12580 or @@ -35157,75 +35226,6 @@ module mkLastLvCRqMshr(CLK, m_dataValidVec_15_dummy2_0_read__2659_AND_m_da_ETC___d12664; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or @@ -35296,72 +35296,72 @@ module mkLastLvCRqMshr(CLK, endcase end always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056) + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019) begin case (sendRsToDmaC_getRq_n) 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11041; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004; 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11042; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005; 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11043; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11006; 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11044; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11007; 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11045; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11008; 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11046; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11009; 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11047; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11010; 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11048; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11011; 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11049; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11012; 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11050; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11013; 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11051; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11014; 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11052; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11015; 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11053; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11016; 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11054; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11017; 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11055; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11018; 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13032 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13029 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11019; endcase end always@(sendRsToDmaC_getRq_n or @@ -35778,75 +35778,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11167; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11170 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11171 or @@ -35916,6 +35847,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11185; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11189; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11190; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11191; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11192; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11193; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11194; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11195; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11196; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11197; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11198; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11199; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11200; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11201; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11202; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11203; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13044 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11204; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11207 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11208 or @@ -36192,6 +36192,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11278; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11281 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11282 or @@ -36330,75 +36399,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11302; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11303; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11304; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11305; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11306; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11307; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11308; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11309; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11310; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11311; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11312; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11313; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11314; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13053 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11337 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11338 or @@ -36675,6 +36675,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11407; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11411 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11412 or @@ -36813,75 +36882,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11463; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13063 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11466 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11467 or @@ -37158,75 +37158,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11537; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or @@ -37296,6 +37227,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11542; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11543; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11544; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11545; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11546; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11547; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11548; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11549; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11550; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11551; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11552; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11553; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11554; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13072 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11555; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11577 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11578 or @@ -37779,75 +37779,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11703; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11707 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11708 or @@ -37917,6 +37848,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11722; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11725; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11726; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11727; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11728; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11729; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11730; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11731; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11732; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11733; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11734; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11735; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11736; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11737; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11738; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11739; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13087 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11740; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11744 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11745 or @@ -38193,6 +38193,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11814; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11818 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11819 or @@ -38262,6 +38331,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11833; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or @@ -38331,75 +38469,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11838; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11839; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11840; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11841; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11842; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11843; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11844; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11845; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11846; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11847; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11848; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11849; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11850; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13096 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11873 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11874 or @@ -38676,6 +38745,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11944; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11947 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11948 or @@ -38814,75 +38952,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11999; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13107 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12003 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12004 or @@ -39159,144 +39228,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092; - endcase - end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12114; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12115; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12116; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12117; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12118; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12119; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12120; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12121; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12122; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12123; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12124; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12125; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12126; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12127; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12128; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13119 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; - endcase - end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or @@ -39366,6 +39297,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12079; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12080; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12081; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12082; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12083; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12084; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12085; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12086; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12087; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12088; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12089; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12090; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12091; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13116 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12092; + endcase + end always@(sendRsToDmaC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12132 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12133 or @@ -39638,6 +39638,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[3]; endcase end + always@(sendRsToDmaC_getData_n or + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673 or + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680 or + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687 or + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694 or + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701 or + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708 or + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715 or + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722 or + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729 or + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736 or + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743 or + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750 or + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757 or + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764 or + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771 or + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778) + begin + case (sendRsToDmaC_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; + endcase + end always@(sendRsToDmaC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10950 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10951 or @@ -39776,75 +39845,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; endcase end - always@(sendRsToDmaC_getData_n or - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673 or - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680 or - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687 or - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694 or - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701 or - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708 or - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715 or - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722 or - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729 or - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736 or - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743 or - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750 or - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757 or - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764 or - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771 or - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778) - begin - case (sendRsToDmaC_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12673; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12680; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12687; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12694; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12701; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12708; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12715; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12722; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12729; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12736; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12743; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12750; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12757; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12764; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12771; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d13141 = - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12778; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12782 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12784 or @@ -40121,6 +40121,75 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; endcase end + always@(sendToM_getData_n or + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851 or + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853 or + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855 or + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857 or + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859 or + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861 or + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863 or + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865 or + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867 or + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869 or + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871 or + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873 or + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875 or + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877 or + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879 or + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881) + begin + case (sendToM_getData_n) + 4'd0: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851; + 4'd1: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853; + 4'd2: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855; + 4'd3: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857; + 4'd4: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859; + 4'd5: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861; + 4'd6: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863; + 4'd7: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865; + 4'd8: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867; + 4'd9: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869; + 4'd10: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871; + 4'd11: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873; + 4'd12: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875; + 4'd13: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877; + 4'd14: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879; + 4'd15: + SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = + IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; + endcase + end always@(sendToM_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12817 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12819 or @@ -40259,75 +40328,6 @@ module mkLastLvCRqMshr(CLK, IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12916; endcase end - always@(sendToM_getData_n or - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851 or - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853 or - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855 or - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857 or - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859 or - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861 or - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863 or - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865 or - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867 or - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869 or - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871 or - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873 or - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875 or - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877 or - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879 or - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881) - begin - case (sendToM_getData_n) - 4'd0: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12851; - 4'd1: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12853; - 4'd2: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_2_dummy2_0_read__2681_AND_m_dataV_ETC___d12855; - 4'd3: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_3_dummy2_0_read__2688_AND_m_dataV_ETC___d12857; - 4'd4: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_4_dummy2_0_read__2695_AND_m_dataV_ETC___d12859; - 4'd5: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_5_dummy2_0_read__2702_AND_m_dataV_ETC___d12861; - 4'd6: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_6_dummy2_0_read__2709_AND_m_dataV_ETC___d12863; - 4'd7: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_7_dummy2_0_read__2716_AND_m_dataV_ETC___d12865; - 4'd8: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_8_dummy2_0_read__2723_AND_m_dataV_ETC___d12867; - 4'd9: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_9_dummy2_0_read__2730_AND_m_dataV_ETC___d12869; - 4'd10: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_10_dummy2_0_read__2737_AND_m_data_ETC___d12871; - 4'd11: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_11_dummy2_0_read__2744_AND_m_data_ETC___d12873; - 4'd12: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_12_dummy2_0_read__2751_AND_m_data_ETC___d12875; - 4'd13: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_13_dummy2_0_read__2758_AND_m_data_ETC___d12877; - 4'd14: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_14_dummy2_0_read__2765_AND_m_data_ETC___d12879; - 4'd15: - SEL_ARR_IF_m_dataVec_0_dummy2_0_read__2667_AND_ETC___d12883 = - IF_m_dataVec_15_dummy2_0_read__2772_AND_m_data_ETC___d12881; - endcase - end always@(sendRsToDmaC_getData_n or IF_m_dataVec_0_dummy2_0_read__2667_AND_m_dataV_ETC___d12920 or IF_m_dataVec_1_dummy2_0_read__2674_AND_m_dataV_ETC___d12922 or @@ -40604,6 +40604,75 @@ module mkLastLvCRqMshr(CLK, m_dataValidVec_15_dummy2_0_read__2659_AND_m_da_ETC___d12664; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11004 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11005 or @@ -40742,75 +40811,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11056; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11022; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11023; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11024; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11025; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11026; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11027; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11028; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11029; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11030; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11031; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11032; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11033; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11034; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11035; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11036; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13177 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11037; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11059 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11060 or @@ -41087,75 +41087,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11130; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11152 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11153 or @@ -41225,6 +41156,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11167; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11133; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11134; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11135; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11136; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11137; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11138; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11139; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11140; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11141; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11142; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11143; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11144; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11145; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11146; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11147; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13186 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11148; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11170 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11171 or @@ -41708,75 +41708,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11296; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11300 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11301 or @@ -41846,6 +41777,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11315; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11318; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11319; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11320; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11321; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11322; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11323; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11324; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11325; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11326; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11327; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11328; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11329; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11330; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11331; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11332; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13201 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11333; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11337 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11338 or @@ -42122,6 +42122,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11407; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11411 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11412 or @@ -42260,75 +42329,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11463; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11429; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11430; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11431; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11432; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11433; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11434; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11435; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11436; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11437; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11438; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11439; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11440; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11441; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11442; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11443; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13210 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11444; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11466 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11467 or @@ -42605,6 +42605,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11537; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11540 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11541 or @@ -42743,75 +42812,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11592; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11559; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11560; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11561; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11562; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11563; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11564; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11565; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11566; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11567; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11568; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11569; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11570; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11571; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11572; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11573; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13221 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11574; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11596 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11597 or @@ -43088,75 +43088,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11666; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11688 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11689 or @@ -43226,6 +43157,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11703; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11670; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11671; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11672; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11673; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11674; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11675; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11676; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11677; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11678; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11679; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11680; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11681; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11682; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11683; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11684; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13230 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11685; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11707 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11708 or @@ -43709,75 +43709,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11833; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11836 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11837 or @@ -43847,6 +43778,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11851; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11855; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11856; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11857; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11858; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11859; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11860; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11861; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11862; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11863; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11864; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11865; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11866; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11867; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11868; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11869; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13245 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11870; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11873 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11874 or @@ -44123,6 +44123,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11944; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11947 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11948 or @@ -44261,75 +44330,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11999; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d11966; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d11967; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d11968; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d11969; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d11970; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d11971; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d11972; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d11973; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d11974; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d11975; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d11976; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d11977; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d11978; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d11979; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d11980; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13254 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d11981; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12003 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12004 or @@ -44606,6 +44606,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12073; endcase end + always@(sendRqToC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110) + begin + case (sendRqToC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12077 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12078 or @@ -44744,75 +44813,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12129; endcase end - always@(sendRqToC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110) - begin - case (sendRqToC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12095; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12096; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12097; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12098; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12099; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12100; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12101; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12102; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12103; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12104; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12105; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12106; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12107; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12108; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12109; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13264 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12110; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12132 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12133 or @@ -46217,122 +46217,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[65]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[63]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[63]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[63]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[63]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[63]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[63]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[63]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[63]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[63]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[63]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[63]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[63]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[63]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[63]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[63]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[63]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46449,6 +46333,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[64]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[63]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[63]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[63]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[63]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[63]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[63]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[63]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[63]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[63]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[63]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[63]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[63]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[63]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[63]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[63]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14071 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[63]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -46913,6 +46913,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[59]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[57]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[57]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[57]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[57]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[57]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[57]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[57]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[57]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[57]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[57]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[57]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[57]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[57]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[57]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[57]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[57]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47145,122 +47261,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[56]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[57]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[57]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[57]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[57]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[57]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[57]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[57]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[57]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[57]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[57]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[57]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[57]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[57]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[57]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[57]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14182 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[57]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47725,6 +47725,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[52]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[50]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[50]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[50]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[50]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[50]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[50]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[50]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[50]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[50]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[50]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[50]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[50]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[50]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[50]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[50]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[50]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -47957,122 +48073,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[49]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[50]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[50]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[50]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[50]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[50]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[50]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[50]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[50]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[50]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[50]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[50]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[50]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[50]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[50]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[50]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14311 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[50]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48537,122 +48537,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[45]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[44]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[44]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[44]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[44]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[44]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[44]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[44]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[44]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[44]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[44]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[44]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[44]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[44]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[44]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[44]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[44]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -48769,6 +48653,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[43]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[44]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[44]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[44]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[44]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[44]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[44]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[44]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[44]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[44]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[44]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[44]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[44]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[44]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[44]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[44]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14422 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[44]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49581,122 +49581,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[36]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[34]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[34]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[34]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[34]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[34]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[34]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[34]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[34]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[34]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[34]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[34]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[34]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[34]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[34]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[34]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[34]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -49813,6 +49697,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[35]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[34]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[34]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[34]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[34]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[34]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[34]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[34]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[34]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[34]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[34]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[34]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[34]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[34]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[34]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[34]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14607 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[34]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50277,6 +50277,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[30]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[28]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[28]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[28]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[28]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[28]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[28]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[28]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[28]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[28]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[28]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[28]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[28]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[28]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[28]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[28]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[28]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -50509,122 +50625,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[27]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[28]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[28]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[28]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[28]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[28]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[28]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[28]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[28]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[28]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[28]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[28]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[28]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[28]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[28]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[28]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14718 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[28]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51089,6 +51089,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[23]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[21]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[21]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[21]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[21]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[21]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[21]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[21]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[21]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[21]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[21]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[21]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[21]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[21]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[21]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[21]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[21]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51321,122 +51437,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[20]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[21]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[21]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[21]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[21]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[21]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[21]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[21]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[21]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[21]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[21]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[21]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[21]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[21]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[21]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[21]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14848 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[21]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -51901,122 +51901,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[16]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_dummy2_1$Q_OUT or - m_reqVec_0_dummy2_2$Q_OUT or - m_reqVec_0_rl or - m_reqVec_1_dummy2_1$Q_OUT or - m_reqVec_1_dummy2_2$Q_OUT or - m_reqVec_1_rl or - m_reqVec_2_dummy2_1$Q_OUT or - m_reqVec_2_dummy2_2$Q_OUT or - m_reqVec_2_rl or - m_reqVec_3_dummy2_1$Q_OUT or - m_reqVec_3_dummy2_2$Q_OUT or - m_reqVec_3_rl or - m_reqVec_4_dummy2_1$Q_OUT or - m_reqVec_4_dummy2_2$Q_OUT or - m_reqVec_4_rl or - m_reqVec_5_dummy2_1$Q_OUT or - m_reqVec_5_dummy2_2$Q_OUT or - m_reqVec_5_rl or - m_reqVec_6_dummy2_1$Q_OUT or - m_reqVec_6_dummy2_2$Q_OUT or - m_reqVec_6_rl or - m_reqVec_7_dummy2_1$Q_OUT or - m_reqVec_7_dummy2_2$Q_OUT or - m_reqVec_7_rl or - m_reqVec_8_dummy2_1$Q_OUT or - m_reqVec_8_dummy2_2$Q_OUT or - m_reqVec_8_rl or - m_reqVec_9_dummy2_1$Q_OUT or - m_reqVec_9_dummy2_2$Q_OUT or - m_reqVec_9_rl or - m_reqVec_10_dummy2_1$Q_OUT or - m_reqVec_10_dummy2_2$Q_OUT or - m_reqVec_10_rl or - m_reqVec_11_dummy2_1$Q_OUT or - m_reqVec_11_dummy2_2$Q_OUT or - m_reqVec_11_rl or - m_reqVec_12_dummy2_1$Q_OUT or - m_reqVec_12_dummy2_2$Q_OUT or - m_reqVec_12_rl or - m_reqVec_13_dummy2_1$Q_OUT or - m_reqVec_13_dummy2_2$Q_OUT or - m_reqVec_13_rl or - m_reqVec_14_dummy2_1$Q_OUT or - m_reqVec_14_dummy2_2$Q_OUT or - m_reqVec_14_rl or - m_reqVec_15_dummy2_1$Q_OUT or - m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && - m_reqVec_0_rl[15]; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && - m_reqVec_1_rl[15]; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && - m_reqVec_2_rl[15]; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && - m_reqVec_3_rl[15]; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && - m_reqVec_4_rl[15]; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && - m_reqVec_5_rl[15]; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && - m_reqVec_6_rl[15]; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && - m_reqVec_7_rl[15]; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && - m_reqVec_8_rl[15]; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && - m_reqVec_9_rl[15]; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && - m_reqVec_10_rl[15]; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && - m_reqVec_11_rl[15]; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && - m_reqVec_12_rl[15]; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && - m_reqVec_13_rl[15]; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && - m_reqVec_14_rl[15]; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = - m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && - m_reqVec_15_rl[15]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52133,6 +52017,122 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_rl[14]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_dummy2_1$Q_OUT or + m_reqVec_0_dummy2_2$Q_OUT or + m_reqVec_0_rl or + m_reqVec_1_dummy2_1$Q_OUT or + m_reqVec_1_dummy2_2$Q_OUT or + m_reqVec_1_rl or + m_reqVec_2_dummy2_1$Q_OUT or + m_reqVec_2_dummy2_2$Q_OUT or + m_reqVec_2_rl or + m_reqVec_3_dummy2_1$Q_OUT or + m_reqVec_3_dummy2_2$Q_OUT or + m_reqVec_3_rl or + m_reqVec_4_dummy2_1$Q_OUT or + m_reqVec_4_dummy2_2$Q_OUT or + m_reqVec_4_rl or + m_reqVec_5_dummy2_1$Q_OUT or + m_reqVec_5_dummy2_2$Q_OUT or + m_reqVec_5_rl or + m_reqVec_6_dummy2_1$Q_OUT or + m_reqVec_6_dummy2_2$Q_OUT or + m_reqVec_6_rl or + m_reqVec_7_dummy2_1$Q_OUT or + m_reqVec_7_dummy2_2$Q_OUT or + m_reqVec_7_rl or + m_reqVec_8_dummy2_1$Q_OUT or + m_reqVec_8_dummy2_2$Q_OUT or + m_reqVec_8_rl or + m_reqVec_9_dummy2_1$Q_OUT or + m_reqVec_9_dummy2_2$Q_OUT or + m_reqVec_9_rl or + m_reqVec_10_dummy2_1$Q_OUT or + m_reqVec_10_dummy2_2$Q_OUT or + m_reqVec_10_rl or + m_reqVec_11_dummy2_1$Q_OUT or + m_reqVec_11_dummy2_2$Q_OUT or + m_reqVec_11_rl or + m_reqVec_12_dummy2_1$Q_OUT or + m_reqVec_12_dummy2_2$Q_OUT or + m_reqVec_12_rl or + m_reqVec_13_dummy2_1$Q_OUT or + m_reqVec_13_dummy2_2$Q_OUT or + m_reqVec_13_rl or + m_reqVec_14_dummy2_1$Q_OUT or + m_reqVec_14_dummy2_2$Q_OUT or + m_reqVec_14_rl or + m_reqVec_15_dummy2_1$Q_OUT or + m_reqVec_15_dummy2_2$Q_OUT or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_0_dummy2_1$Q_OUT && m_reqVec_0_dummy2_2$Q_OUT && + m_reqVec_0_rl[15]; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_1_dummy2_1$Q_OUT && m_reqVec_1_dummy2_2$Q_OUT && + m_reqVec_1_rl[15]; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_2_dummy2_1$Q_OUT && m_reqVec_2_dummy2_2$Q_OUT && + m_reqVec_2_rl[15]; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_3_dummy2_1$Q_OUT && m_reqVec_3_dummy2_2$Q_OUT && + m_reqVec_3_rl[15]; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_4_dummy2_1$Q_OUT && m_reqVec_4_dummy2_2$Q_OUT && + m_reqVec_4_rl[15]; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_5_dummy2_1$Q_OUT && m_reqVec_5_dummy2_2$Q_OUT && + m_reqVec_5_rl[15]; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_6_dummy2_1$Q_OUT && m_reqVec_6_dummy2_2$Q_OUT && + m_reqVec_6_rl[15]; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_7_dummy2_1$Q_OUT && m_reqVec_7_dummy2_2$Q_OUT && + m_reqVec_7_rl[15]; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_8_dummy2_1$Q_OUT && m_reqVec_8_dummy2_2$Q_OUT && + m_reqVec_8_rl[15]; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_9_dummy2_1$Q_OUT && m_reqVec_9_dummy2_2$Q_OUT && + m_reqVec_9_rl[15]; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_10_dummy2_1$Q_OUT && m_reqVec_10_dummy2_2$Q_OUT && + m_reqVec_10_rl[15]; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_11_dummy2_1$Q_OUT && m_reqVec_11_dummy2_2$Q_OUT && + m_reqVec_11_rl[15]; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_12_dummy2_1$Q_OUT && m_reqVec_12_dummy2_2$Q_OUT && + m_reqVec_12_rl[15]; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_13_dummy2_1$Q_OUT && m_reqVec_13_dummy2_2$Q_OUT && + m_reqVec_13_rl[15]; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_14_dummy2_1$Q_OUT && m_reqVec_14_dummy2_2$Q_OUT && + m_reqVec_14_rl[15]; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_1_read__0851_AND_m_r_ETC___d14959 = + m_reqVec_15_dummy2_1$Q_OUT && m_reqVec_15_dummy2_2$Q_OUT && + m_reqVec_15_rl[15]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -52945,73 +52945,6 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[5]; endcase end - always@(pipelineResp_getRq_n or - m_reqVec_0_rl or - m_reqVec_1_rl or - m_reqVec_2_rl or - m_reqVec_3_rl or - m_reqVec_4_rl or - m_reqVec_5_rl or - m_reqVec_6_rl or - m_reqVec_7_rl or - m_reqVec_8_rl or - m_reqVec_9_rl or - m_reqVec_10_rl or - m_reqVec_11_rl or - m_reqVec_12_rl or - m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_0_rl[3]; - 4'd1: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_1_rl[3]; - 4'd2: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_2_rl[3]; - 4'd3: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_3_rl[3]; - 4'd4: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_4_rl[3]; - 4'd5: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_5_rl[3]; - 4'd6: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_6_rl[3]; - 4'd7: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_7_rl[3]; - 4'd8: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_8_rl[3]; - 4'd9: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_9_rl[3]; - 4'd10: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_10_rl[3]; - 4'd11: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_11_rl[3]; - 4'd12: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_12_rl[3]; - 4'd13: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_13_rl[3]; - 4'd14: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_14_rl[3]; - 4'd15: - SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = - m_reqVec_15_rl[3]; - endcase - end always@(pipelineResp_getRq_n or m_reqVec_0_rl or m_reqVec_1_rl or @@ -53079,6 +53012,73 @@ module mkLastLvCRqMshr(CLK, !m_reqVec_15_rl[4]; endcase end + always@(pipelineResp_getRq_n or + m_reqVec_0_rl or + m_reqVec_1_rl or + m_reqVec_2_rl or + m_reqVec_3_rl or + m_reqVec_4_rl or + m_reqVec_5_rl or + m_reqVec_6_rl or + m_reqVec_7_rl or + m_reqVec_8_rl or + m_reqVec_9_rl or + m_reqVec_10_rl or + m_reqVec_11_rl or + m_reqVec_12_rl or + m_reqVec_13_rl or m_reqVec_14_rl or m_reqVec_15_rl) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_0_rl[3]; + 4'd1: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_1_rl[3]; + 4'd2: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_2_rl[3]; + 4'd3: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_3_rl[3]; + 4'd4: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_4_rl[3]; + 4'd5: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_5_rl[3]; + 4'd6: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_6_rl[3]; + 4'd7: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_7_rl[3]; + 4'd8: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_8_rl[3]; + 4'd9: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_9_rl[3]; + 4'd10: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_10_rl[3]; + 4'd11: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_11_rl[3]; + 4'd12: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_12_rl[3]; + 4'd13: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_13_rl[3]; + 4'd14: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_14_rl[3]; + 4'd15: + SEL_ARR_IF_m_reqVec_0_lat_0_whas_THEN_m_reqVec_ETC___d15185 = + m_reqVec_15_rl[3]; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -54451,75 +54451,6 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12166; endcase end - always@(sendRsToDmaC_getRq_n or - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171 or - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172 or - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173 or - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174 or - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175 or - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176 or - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177 or - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178 or - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179 or - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180 or - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181 or - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182 or - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183 or - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184) - begin - case (sendRsToDmaC_getRq_n) - 4'd0: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169; - 4'd1: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170; - 4'd2: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171; - 4'd3: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172; - 4'd4: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173; - 4'd5: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174; - 4'd6: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175; - 4'd7: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176; - 4'd8: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177; - 4'd9: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178; - 4'd10: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179; - 4'd11: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180; - 4'd12: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181; - 4'd13: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182; - 4'd14: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183; - 4'd15: - SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = - m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184; - endcase - end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12151 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12152 or @@ -54589,6 +54520,75 @@ module mkLastLvCRqMshr(CLK, m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12166; endcase end + always@(sendRsToDmaC_getRq_n or + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171 or + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172 or + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173 or + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174 or + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175 or + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176 or + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177 or + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178 or + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179 or + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180 or + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181 or + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182 or + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183 or + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184) + begin + case (sendRsToDmaC_getRq_n) + 4'd0: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169; + 4'd1: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170; + 4'd2: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_2_dummy2_0_read__0860_AND_m_reqVec_2__ETC___d12171; + 4'd3: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_3_dummy2_0_read__0865_AND_m_reqVec_3__ETC___d12172; + 4'd4: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_4_dummy2_0_read__0870_AND_m_reqVec_4__ETC___d12173; + 4'd5: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_5_dummy2_0_read__0875_AND_m_reqVec_5__ETC___d12174; + 4'd6: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_6_dummy2_0_read__0880_AND_m_reqVec_6__ETC___d12175; + 4'd7: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_7_dummy2_0_read__0885_AND_m_reqVec_7__ETC___d12176; + 4'd8: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_8_dummy2_0_read__0890_AND_m_reqVec_8__ETC___d12177; + 4'd9: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_9_dummy2_0_read__0895_AND_m_reqVec_9__ETC___d12178; + 4'd10: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_10_dummy2_0_read__0900_AND_m_reqVec_1_ETC___d12179; + 4'd11: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_11_dummy2_0_read__0905_AND_m_reqVec_1_ETC___d12180; + 4'd12: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_12_dummy2_0_read__0910_AND_m_reqVec_1_ETC___d12181; + 4'd13: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_13_dummy2_0_read__0915_AND_m_reqVec_1_ETC___d12182; + 4'd14: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_14_dummy2_0_read__0920_AND_m_reqVec_1_ETC___d12183; + 4'd15: + SEL_ARR_m_reqVec_0_dummy2_0_read__0850_AND_m_r_ETC___d13123 = + m_reqVec_15_dummy2_0_read__0925_AND_m_reqVec_1_ETC___d12184; + endcase + end always@(sendRqToC_getRq_n or m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_0__ETC___d12169 or m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_1__ETC___d12170 or @@ -56065,74 +56065,6 @@ module mkLastLvCRqMshr(CLK, n__read_addr__h899290; endcase end - always@(pipelineResp_getRq_n or - n__read_addr__h995902 or - n__read_addr__h996004 or - n__read_addr__h996106 or - n__read_addr__h996208 or - n__read_addr__h996310 or - n__read_addr__h996412 or - n__read_addr__h996514 or - n__read_addr__h996616 or - n__read_addr__h996718 or - n__read_addr__h996820 or - n__read_addr__h996922 or - n__read_addr__h997024 or - n__read_addr__h997126 or - n__read_addr__h997228 or - n__read_addr__h997330 or n__read_addr__h997432) - begin - case (pipelineResp_getRq_n) - 4'd0: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h995902; - 4'd1: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996004; - 4'd2: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996106; - 4'd3: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996208; - 4'd4: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996310; - 4'd5: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996412; - 4'd6: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996514; - 4'd7: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996616; - 4'd8: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996718; - 4'd9: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996820; - 4'd10: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h996922; - 4'd11: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997024; - 4'd12: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997126; - 4'd13: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997228; - 4'd14: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997330; - 4'd15: - SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = - n__read_addr__h997432; - endcase - end always@(sendRqToC_getRq_n or IF_m_reqVec_0_dummy2_0_read__0850_AND_m_reqVec_ETC___d10932 or IF_m_reqVec_1_dummy2_0_read__0855_AND_m_reqVec_ETC___d10933 or @@ -56202,6 +56134,74 @@ module mkLastLvCRqMshr(CLK, IF_m_reqVec_15_dummy2_0_read__0925_AND_m_reqVe_ETC___d10947; endcase end + always@(pipelineResp_getRq_n or + n__read_addr__h995902 or + n__read_addr__h996004 or + n__read_addr__h996106 or + n__read_addr__h996208 or + n__read_addr__h996310 or + n__read_addr__h996412 or + n__read_addr__h996514 or + n__read_addr__h996616 or + n__read_addr__h996718 or + n__read_addr__h996820 or + n__read_addr__h996922 or + n__read_addr__h997024 or + n__read_addr__h997126 or + n__read_addr__h997228 or + n__read_addr__h997330 or n__read_addr__h997432) + begin + case (pipelineResp_getRq_n) + 4'd0: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h995902; + 4'd1: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996004; + 4'd2: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996106; + 4'd3: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996208; + 4'd4: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996310; + 4'd5: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996412; + 4'd6: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996514; + 4'd7: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996616; + 4'd8: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996718; + 4'd9: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996820; + 4'd10: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h996922; + 4'd11: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997024; + 4'd12: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997126; + 4'd13: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997228; + 4'd14: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997330; + 4'd15: + SEL_ARR_IF_m_reqVec_0_dummy2_1_read__0851_AND__ETC___d13870 = + n__read_addr__h997432; + endcase + end always@(pipelineResp_getRq_n or m_reqVec_0_dummy2_1$Q_OUT or m_reqVec_0_dummy2_2$Q_OUT or @@ -57504,107 +57504,6 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3268; endcase end - always@(transfer_getSlot_n or - m_slotVec_0_dummy2_2$Q_OUT or - IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931 or - m_slotVec_1_dummy2_2$Q_OUT or - IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018 or - m_slotVec_2_dummy2_2$Q_OUT or - IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104 or - m_slotVec_3_dummy2_2$Q_OUT or - IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190 or - m_slotVec_4_dummy2_2$Q_OUT or - IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276 or - m_slotVec_5_dummy2_2$Q_OUT or - IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362 or - m_slotVec_6_dummy2_2$Q_OUT or - IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448 or - m_slotVec_7_dummy2_2$Q_OUT or - IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534 or - m_slotVec_8_dummy2_2$Q_OUT or - IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620 or - m_slotVec_9_dummy2_2$Q_OUT or - IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706 or - m_slotVec_10_dummy2_2$Q_OUT or - IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792 or - m_slotVec_11_dummy2_2$Q_OUT or - IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878 or - m_slotVec_12_dummy2_2$Q_OUT or - IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964 or - m_slotVec_13_dummy2_2$Q_OUT or - IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050 or - m_slotVec_14_dummy2_2$Q_OUT or - IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136 or - m_slotVec_15_dummy2_2$Q_OUT or - IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222) - begin - case (transfer_getSlot_n) - 4'd0: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_0_dummy2_2$Q_OUT && - IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931; - 4'd1: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_1_dummy2_2$Q_OUT && - IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018; - 4'd2: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_2_dummy2_2$Q_OUT && - IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104; - 4'd3: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_3_dummy2_2$Q_OUT && - IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190; - 4'd4: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_4_dummy2_2$Q_OUT && - IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276; - 4'd5: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_5_dummy2_2$Q_OUT && - IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362; - 4'd6: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_6_dummy2_2$Q_OUT && - IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448; - 4'd7: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_7_dummy2_2$Q_OUT && - IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534; - 4'd8: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_8_dummy2_2$Q_OUT && - IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620; - 4'd9: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_9_dummy2_2$Q_OUT && - IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706; - 4'd10: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_10_dummy2_2$Q_OUT && - IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792; - 4'd11: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_11_dummy2_2$Q_OUT && - IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878; - 4'd12: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_12_dummy2_2$Q_OUT && - IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964; - 4'd13: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_13_dummy2_2$Q_OUT && - IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050; - 4'd14: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_14_dummy2_2$Q_OUT && - IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136; - 4'd15: - SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = - m_slotVec_15_dummy2_2$Q_OUT && - IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222; - endcase - end always@(transfer_getSlot_n or m_slotVec_0_dummy2_2$Q_OUT or IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1971 or @@ -57706,6 +57605,107 @@ module mkLastLvCRqMshr(CLK, IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3261; endcase end + always@(transfer_getSlot_n or + m_slotVec_0_dummy2_2$Q_OUT or + IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931 or + m_slotVec_1_dummy2_2$Q_OUT or + IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018 or + m_slotVec_2_dummy2_2$Q_OUT or + IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104 or + m_slotVec_3_dummy2_2$Q_OUT or + IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190 or + m_slotVec_4_dummy2_2$Q_OUT or + IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276 or + m_slotVec_5_dummy2_2$Q_OUT or + IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362 or + m_slotVec_6_dummy2_2$Q_OUT or + IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448 or + m_slotVec_7_dummy2_2$Q_OUT or + IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534 or + m_slotVec_8_dummy2_2$Q_OUT or + IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620 or + m_slotVec_9_dummy2_2$Q_OUT or + IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706 or + m_slotVec_10_dummy2_2$Q_OUT or + IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792 or + m_slotVec_11_dummy2_2$Q_OUT or + IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878 or + m_slotVec_12_dummy2_2$Q_OUT or + IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964 or + m_slotVec_13_dummy2_2$Q_OUT or + IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050 or + m_slotVec_14_dummy2_2$Q_OUT or + IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136 or + m_slotVec_15_dummy2_2$Q_OUT or + IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222) + begin + case (transfer_getSlot_n) + 4'd0: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_0_dummy2_2$Q_OUT && + IF_m_slotVec_0_lat_1_whas__908_THEN_m_slotVec__ETC___d1931; + 4'd1: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_1_dummy2_2$Q_OUT && + IF_m_slotVec_1_lat_1_whas__995_THEN_m_slotVec__ETC___d2018; + 4'd2: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_2_dummy2_2$Q_OUT && + IF_m_slotVec_2_lat_1_whas__081_THEN_m_slotVec__ETC___d2104; + 4'd3: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_3_dummy2_2$Q_OUT && + IF_m_slotVec_3_lat_1_whas__167_THEN_m_slotVec__ETC___d2190; + 4'd4: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_4_dummy2_2$Q_OUT && + IF_m_slotVec_4_lat_1_whas__253_THEN_m_slotVec__ETC___d2276; + 4'd5: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_5_dummy2_2$Q_OUT && + IF_m_slotVec_5_lat_1_whas__339_THEN_m_slotVec__ETC___d2362; + 4'd6: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_6_dummy2_2$Q_OUT && + IF_m_slotVec_6_lat_1_whas__425_THEN_m_slotVec__ETC___d2448; + 4'd7: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_7_dummy2_2$Q_OUT && + IF_m_slotVec_7_lat_1_whas__511_THEN_m_slotVec__ETC___d2534; + 4'd8: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_8_dummy2_2$Q_OUT && + IF_m_slotVec_8_lat_1_whas__597_THEN_m_slotVec__ETC___d2620; + 4'd9: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_9_dummy2_2$Q_OUT && + IF_m_slotVec_9_lat_1_whas__683_THEN_m_slotVec__ETC___d2706; + 4'd10: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_10_dummy2_2$Q_OUT && + IF_m_slotVec_10_lat_1_whas__769_THEN_m_slotVec_ETC___d2792; + 4'd11: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_11_dummy2_2$Q_OUT && + IF_m_slotVec_11_lat_1_whas__855_THEN_m_slotVec_ETC___d2878; + 4'd12: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_12_dummy2_2$Q_OUT && + IF_m_slotVec_12_lat_1_whas__941_THEN_m_slotVec_ETC___d2964; + 4'd13: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_13_dummy2_2$Q_OUT && + IF_m_slotVec_13_lat_1_whas__027_THEN_m_slotVec_ETC___d3050; + 4'd14: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_14_dummy2_2$Q_OUT && + IF_m_slotVec_14_lat_1_whas__113_THEN_m_slotVec_ETC___d3136; + 4'd15: + SEL_ARR_m_slotVec_0_dummy2_2_read__0613_AND_IF_ETC___d10682 = + m_slotVec_15_dummy2_2$Q_OUT && + IF_m_slotVec_15_lat_1_whas__199_THEN_m_slotVec_ETC___d3222; + endcase + end always@(transfer_getSlot_n or n__read_repTag__h680626 or n__read_repTag__h680836 or diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v index 530ef3b..fbe2286 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v @@ -388,8 +388,8 @@ module mkMMIOInst(CLK, // value method getFetchTarget assign getFetchTarget = - (getFetchTarget_phyPc[63:3] >= 61'd512 && - getFetchTarget_phyPc[63:3] < 61'd1024) ? + (getFetchTarget_phyPc[63:3] >= 61'd234881024 && + getFetchTarget_phyPc[63:3] < 61'd234881536) ? 2'd1 : IF_NOT_getFetchTarget_phyPc_BITS_63_TO_3_61_UL_ETC___d276 ; assign RDY_getFetchTarget = 1'd1 ; @@ -840,7 +840,7 @@ module mkMMIOInst(CLK, // remaining internal signals assign IF_NOT_getFetchTarget_phyPc_BITS_63_TO_3_61_UL_ETC___d276 = - (getFetchTarget_phyPc[63:3] >= 61'd268435456 && + (getFetchTarget_phyPc[63:3] >= 61'd402653184 && getFetchTarget_phyPc[63:3] != toHostAddr && getFetchTarget_phyPc[63:3] != fromHostAddr) ? 2'd0 : diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v index cf79c52..aa5593b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v @@ -177,7 +177,6 @@ module mkMemLoader(CLK_portalClk, // inlined wires wire [640 : 0] memReqQ_enqReq_lat_0$wget; - wire memReqQ_enqReq_lat_0$whas; // register busy reg busy; @@ -656,6 +655,7 @@ module mkMemLoader(CLK_portalClk, wire MUX_busy$write_1__SEL_1, MUX_busy$write_1__SEL_2, MUX_expectWrData$write_1__SEL_1, + MUX_pendStCnt$write_1__SEL_2, MUX_writing$write_1__SEL_2; // remaining internal signals @@ -677,11 +677,11 @@ module mkMemLoader(CLK_portalClk, wire [31 : 0] IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187, IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41, IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11, + IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114, IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84, IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260, IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230, IF_mmio_req_wrBE_BIT_7_67_THEN_mmio_req_wrData_ETC___d993, - x__h4676, x__h6528; wire [7 : 0] IF_reqSel_70_EQ_0_77_THEN_hostWrDataQ_q_wDataO_ETC___d481, IF_reqSel_70_EQ_1_98_THEN_hostWrDataQ_q_wDataO_ETC___d500, @@ -1317,6 +1317,9 @@ module mkMemLoader(CLK_portalClk, mmio_req_wrBE_BIT_0_60_OR_mmio_req_wrBE_BIT_1__ETC___d978 ; assign MUX_expectWrData$write_1__SEL_1 = WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ; + assign MUX_pendStCnt$write_1__SEL_2 = + WILL_FIRE_RL_doStReq && + reqSel_70_EQ_7_71_OR_hostWrDataQ_q_wDataOut_wg_ETC___d930 ; assign MUX_writing$write_1__SEL_2 = WILL_FIRE_RL_doStResp && pendStCnt == 8'd1 && !expectWrData ; assign MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1 = @@ -1336,7 +1339,7 @@ module mkMemLoader(CLK_portalClk, hostWrAddrQ_q_rWrPtr_rsCounter | x__h938 : hostWrAddrQ_q_rWrPtr_rsCounter & y__h1133 ; assign MUX_hostWrDataQ_q_rRdPtr_rsCounter$write_1__VAL_1 = - (~hostWrDataQ_q_rRdPtr_rsCounter[x__h4676[0]]) ? + (~hostWrDataQ_q_rRdPtr_rsCounter[IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114[0]]) ? hostWrDataQ_q_rRdPtr_rsCounter | x__h4511 : hostWrDataQ_q_rRdPtr_rsCounter & y__h4698 ; assign MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 = @@ -1388,9 +1391,6 @@ module mkMemLoader(CLK_portalClk, IF_reqSel_70_EQ_2_17_THEN_hostWrDataQ_q_wDataO_ETC___d721, IF_reqSel_70_EQ_1_98_THEN_hostWrDataQ_q_wDataO_ETC___d724, IF_reqSel_70_EQ_0_77_THEN_hostWrDataQ_q_wDataO_ETC___d726 } ; - assign memReqQ_enqReq_lat_0$whas = - WILL_FIRE_RL_doStReq && - reqSel_70_EQ_7_71_OR_hostWrDataQ_q_wDataOut_wg_ETC___d930 ; // register busy assign busy$D_IN = !MUX_busy$write_1__SEL_1 ; @@ -1533,7 +1533,7 @@ module mkMemLoader(CLK_portalClk, // register memReqQ_data_0 assign memReqQ_data_0$D_IN = { x_addr__h43806, - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[575:0] : memReqQ_enqReq_rl[575:0] } ; assign memReqQ_data_0$EN = @@ -1568,13 +1568,13 @@ module mkMemLoader(CLK_portalClk, // register pendStCnt always@(MUX_expectWrData$write_1__SEL_1 or - memReqQ_enqReq_lat_0$whas or + MUX_pendStCnt$write_1__SEL_2 or MUX_pendStCnt$write_1__VAL_2 or WILL_FIRE_RL_doStResp or MUX_pendStCnt$write_1__VAL_3) begin case (1'b1) // synopsys parallel_case MUX_expectWrData$write_1__SEL_1: pendStCnt$D_IN = 8'd0; - memReqQ_enqReq_lat_0$whas: + MUX_pendStCnt$write_1__SEL_2: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_2; WILL_FIRE_RL_doStResp: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_3; default: pendStCnt$D_IN = 8'b10101010 /* unspecified value */ ; @@ -1743,7 +1743,7 @@ module mkMemLoader(CLK_portalClk, // submodule memReqQ_enqReq_dummy2_0 assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ; - assign memReqQ_enqReq_dummy2_0$EN = memReqQ_enqReq_lat_0$whas ; + assign memReqQ_enqReq_dummy2_0$EN = MUX_pendStCnt$write_1__SEL_2 ; // submodule memReqQ_enqReq_dummy2_1 assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ; @@ -1798,6 +1798,10 @@ module mkMemLoader(CLK_portalClk, hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10 ? 32'd1 : 32'd0 ; + assign IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 = + hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? + 32'd1 : + 32'd0 ; assign IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 = hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ? 32'd1 : @@ -1811,7 +1815,7 @@ module mkMemLoader(CLK_portalClk, 32'd1 : 32'd0 ; assign IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[640] : memReqQ_enqReq_rl[640] ; assign IF_mmio_req_wrBE_BIT_7_67_THEN_mmio_req_wrData_ETC___d1000 = @@ -2045,7 +2049,7 @@ module mkMemLoader(CLK_portalClk, !memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ; assign NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366 = (!memReqQ_enqReq_dummy2_2$Q_OUT || - (memReqQ_enqReq_lat_0$whas ? + (MUX_pendStCnt$write_1__SEL_2 ? !memReqQ_enqReq_lat_0$wget[640] : !memReqQ_enqReq_rl[640])) && (memReqQ_deqReq_dummy2_2$Q_OUT && @@ -2153,11 +2157,9 @@ module mkMemLoader(CLK_portalClk, assign x__h3656 = 2'd1 << IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 ; - assign x__h4511 = 2'd1 << x__h4676 ; - assign x__h4676 = - hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ? - 32'd1 : - 32'd0 ; + assign x__h4511 = + 2'd1 << + IF_hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11__ETC___d114 ; assign x__h5470 = x_sReadBin__h4920 + 2'd1 ; assign x__h6363 = 2'd1 << x__h6528 ; assign x__h6528 = @@ -2178,7 +2180,7 @@ module mkMemLoader(CLK_portalClk, 2'd1 << IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 ; assign x_addr__h43806 = - memReqQ_enqReq_lat_0$whas ? + MUX_pendStCnt$write_1__SEL_2 ? memReqQ_enqReq_lat_0$wget[639:576] : memReqQ_enqReq_rl[639:576] ; assign x_dReadBin__h10337 = diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index e01a625..58ecfaa 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -683,6 +683,8 @@ module mkP3_Core(CLK, corew$cpu_imem_master_awaddr, corew$cpu_imem_master_rdata, corew$cpu_imem_master_wdata, + corew$set_htif_addrs_fromhost_addr, + corew$set_htif_addrs_tohost_addr, corew$set_verbosity_logdelay; wire [31 : 0] corew$dm_dmi_read_data, corew$dm_dmi_write_dm_word; wire [7 : 0] corew$cpu_dmem_master_arlen, @@ -737,6 +739,7 @@ module mkP3_Core(CLK, corew$EN_dm_dmi_read_data, corew$EN_dm_dmi_write, corew$EN_dm_ndm_reset_req_get_get, + corew$EN_set_htif_addrs, corew$EN_set_verbosity, corew$EN_tv_verifier_info_get_get, corew$RDY_cpu_reset_server_request_put, @@ -1228,9 +1231,12 @@ module mkP3_Core(CLK, .dm_dmi_read_addr_dm_addr(corew$dm_dmi_read_addr_dm_addr), .dm_dmi_write_dm_addr(corew$dm_dmi_write_dm_addr), .dm_dmi_write_dm_word(corew$dm_dmi_write_dm_word), + .set_htif_addrs_fromhost_addr(corew$set_htif_addrs_fromhost_addr), + .set_htif_addrs_tohost_addr(corew$set_htif_addrs_tohost_addr), .set_verbosity_logdelay(corew$set_verbosity_logdelay), .set_verbosity_verbosity(corew$set_verbosity_verbosity), .EN_set_verbosity(corew$EN_set_verbosity), + .EN_set_htif_addrs(corew$EN_set_htif_addrs), .EN_cpu_reset_server_request_put(corew$EN_cpu_reset_server_request_put), .EN_cpu_reset_server_response_get(corew$EN_cpu_reset_server_response_get), .EN_tv_verifier_info_get_get(corew$EN_tv_verifier_info_get_get), @@ -1239,6 +1245,7 @@ module mkP3_Core(CLK, .EN_dm_dmi_write(corew$EN_dm_dmi_write), .EN_dm_ndm_reset_req_get_get(corew$EN_dm_ndm_reset_req_get_get), .RDY_set_verbosity(), + .RDY_set_htif_addrs(), .RDY_cpu_reset_server_request_put(corew$RDY_cpu_reset_server_request_put), .RDY_cpu_reset_server_response_get(corew$RDY_cpu_reset_server_response_get), .cpu_imem_master_awvalid(corew$cpu_imem_master_awvalid), @@ -1624,9 +1631,12 @@ module mkP3_Core(CLK, assign corew$dm_dmi_read_addr_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dm_dmi_write_dm_addr = bus_dmi_req_fifof$D_OUT[40:34] ; assign corew$dm_dmi_write_dm_word = bus_dmi_req_fifof$D_OUT[33:2] ; + assign corew$set_htif_addrs_fromhost_addr = 64'h0 ; + assign corew$set_htif_addrs_tohost_addr = 64'h0 ; assign corew$set_verbosity_logdelay = 64'h0 ; assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$EN_set_verbosity = 1'b0 ; + assign corew$EN_set_htif_addrs = 1'b0 ; assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; assign corew$EN_cpu_reset_server_response_get = corew$RDY_cpu_reset_server_response_get ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 1f11162..5d14a08 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -1875,60 +1875,60 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h64898; - reg [63 : 0] v__h65518; - reg [63 : 0] v__h66335; - reg [63 : 0] v__h85916; - reg [63 : 0] v__h86536; - reg [63 : 0] v__h88783; - reg [63 : 0] v__h99220; - reg [63 : 0] v__h99988; - reg [31 : 0] v__h4974; - reg [31 : 0] v__h5140; - reg [31 : 0] v__h5418; - reg [31 : 0] v__h7457; - reg [31 : 0] v__h3250; - reg [31 : 0] v__h7758; - reg [31 : 0] v__h8249; - reg [31 : 0] v__h8412; - reg [31 : 0] v__h139957; - reg [31 : 0] v__h140124; - reg [31 : 0] v__h142227; - reg [31 : 0] v__h159573; - reg [31 : 0] v__h139339; - reg [31 : 0] v__h166268; - reg [31 : 0] v__h166776; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4968; - reg [31 : 0] v__h5134; - reg [31 : 0] v__h5412; - reg [31 : 0] v__h7451; - reg [31 : 0] v__h7752; - reg [31 : 0] v__h8243; - reg [31 : 0] v__h8406; - reg [31 : 0] v__h139333; - reg [31 : 0] v__h139951; - reg [31 : 0] v__h140118; - reg [31 : 0] v__h142221; - reg [31 : 0] v__h159567; - reg [31 : 0] v__h166262; - reg [31 : 0] v__h166770; + reg [63 : 0] v__h64914; + reg [63 : 0] v__h65534; + reg [63 : 0] v__h66351; + reg [63 : 0] v__h85932; + reg [63 : 0] v__h86552; + reg [63 : 0] v__h88799; + reg [63 : 0] v__h99236; + reg [63 : 0] v__h100004; + reg [31 : 0] v__h4988; + reg [31 : 0] v__h5154; + reg [31 : 0] v__h5432; + reg [31 : 0] v__h7471; + reg [31 : 0] v__h3264; + reg [31 : 0] v__h7772; + reg [31 : 0] v__h8263; + reg [31 : 0] v__h8426; + reg [31 : 0] v__h139973; + reg [31 : 0] v__h140140; + reg [31 : 0] v__h142243; + reg [31 : 0] v__h159589; + reg [31 : 0] v__h139355; + reg [31 : 0] v__h166284; + reg [31 : 0] v__h166792; + reg [31 : 0] v__h3258; + reg [31 : 0] v__h4982; + reg [31 : 0] v__h5148; + reg [31 : 0] v__h5426; + reg [31 : 0] v__h7465; + reg [31 : 0] v__h7766; + reg [31 : 0] v__h8257; + reg [31 : 0] v__h8420; + reg [31 : 0] v__h139349; + reg [31 : 0] v__h139967; + reg [31 : 0] v__h140134; + reg [31 : 0] v__h142237; + reg [31 : 0] v__h159583; + reg [31 : 0] v__h166278; + reg [31 : 0] v__h166786; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26, - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26, + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087, @@ -1938,34 +1938,34 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145, IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113, IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115, - data64__h153397, - ld_data__h136445, - w1__h50197, - w1__h50202, - w2__h50198, - w2__h50204, - x__h50193; + data64__h153413, + ld_data__h136461, + w1__h50213, + w1__h50218, + w2__h50214, + w2__h50220, + x__h50209; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1211; - reg [7 : 0] strb8__h153398; + reg [7 : 0] strb8__h153414; reg [5 : 0] IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_ETC___d608; - reg [2 : 0] x__h64212; - reg [1 : 0] CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14; + reg [2 : 0] x__h64228; + reg [1 : 0] CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12, + CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_IF_ETC___d1318, SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_AND__ETC___d1633, - x__h64219, - x__h85239; + x__h64235, + x__h85255; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1584; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1583; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725, - new_cline__h140260; + new_cline__h140276; wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708; wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674; @@ -1986,84 +1986,84 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_1_ETC___d781, IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1469, IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1507, - data__h31864, - failed_testnum__h168166, - mem_req_rd_addr_araddr__h139558, - mem_req_wr_addr_awaddr__h153482, - mmioPlatform_fromHostQ_data_0__h43716, - mmioPlatform_mtime__h37701, - mmioPlatform_reqData__h50789, - n__read_addr__h64080, - n__read_addr__h64165, - n__read_addr__h83001, - n__read_addr__h83080, - n__read_snd_addr__h98573, - newData__h31946, - newData__h35396, - op_result__h50805, - op_result__h51335, - op_result__h51340, - op_result__h51345, - op_result__h51350, + data__h31881, + failed_testnum__h168182, + mem_req_rd_addr_araddr__h139574, + mem_req_wr_addr_awaddr__h153498, + mmioPlatform_fromHostQ_data_0__h43732, + mmioPlatform_mtime__h37718, + mmioPlatform_reqData__h50805, + n__read_addr__h64096, + n__read_addr__h64181, + n__read_addr__h83017, + n__read_addr__h83096, + n__read_snd_addr__h98589, + newData__h31963, + newData__h35413, + op_result__h50821, + op_result__h51351, op_result__h51356, - op_result__h51363, - op_result__h51369, - result__h50248, - result__h50372, - result__h50400, - result__h50428, - result__h50456, - result__h50484, - result__h50512, - result__h50540, - result__h50568, - result__h50613, - result__h50641, - result__h50669, - result__h50697, - result__h50738, - result__h50766, - result__h50892, - result__h50919, - result__h50946, - result__h50973, - result__h51000, - result__h51027, - result__h51054, - result__h51081, - result__h51125, - result__h51152, - result__h51179, - result__h51206, - result__h51246, - result__h51273, - result__h51390, - result__h51456, - result__h51522, - result__h51588, - result__h51654, - result__h51720, - result__h51786, - result__h51848, - result__h51893, - result__h51959, - result__h52025, - result__h52083, - result__h52128, - value__h38933, - w1___1__h50307, - w2___1__h50308, - x1_avValue_data__h41372, - x1_avValue_data__h41382, - x1_avValue_data__h45993, - x1_avValue_data__h46003, - x__h32057, - x__h35487, - x__h41906, - x__h41917, - x__h43972, - x__h43983, - x__h52305; + op_result__h51361, + op_result__h51366, + op_result__h51372, + op_result__h51379, + op_result__h51385, + result__h50264, + result__h50388, + result__h50416, + result__h50444, + result__h50472, + result__h50500, + result__h50528, + result__h50556, + result__h50584, + result__h50629, + result__h50657, + result__h50685, + result__h50713, + result__h50754, + result__h50782, + result__h50908, + result__h50935, + result__h50962, + result__h50989, + result__h51016, + result__h51043, + result__h51070, + result__h51097, + result__h51141, + result__h51168, + result__h51195, + result__h51222, + result__h51262, + result__h51289, + result__h51406, + result__h51472, + result__h51538, + result__h51604, + result__h51670, + result__h51736, + result__h51802, + result__h51864, + result__h51909, + result__h51975, + result__h52041, + result__h52099, + result__h52144, + value__h38950, + w1___1__h50323, + w2___1__h50324, + x1_avValue_data__h41388, + x1_avValue_data__h41398, + x1_avValue_data__h46009, + x1_avValue_data__h46019, + x__h32074, + x__h35504, + x__h41922, + x__h41933, + x__h43988, + x__h43999, + x__h52321; wire [47 : 0] IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d675, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d748, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d865; @@ -2071,22 +2071,22 @@ module mkProc(CLK, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d666, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d743, IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d860, - lower_data__h31801, + lower_data__h31818, mmioPlatform_mtime_BITS_31_TO_0__q4, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - upper_data__h31802, - v__h31657, - v__h31694, - w10197_BITS_31_TO_0__q7, - w20198_BITS_31_TO_0__q8, - x_data__h30443; + upper_data__h31819, + v__h31674, + v__h31711, + w10213_BITS_31_TO_0__q7, + w20214_BITS_31_TO_0__q8, + x_data__h30460; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389; - wire [5 : 0] x__h139593, x__h153507; + wire [5 : 0] x__h139609, x__h153523; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388; - wire [3 : 0] b__h139266, b__h3144; - wire [2 : 0] n__read_id__h64084, n__read_id__h64169; + wire [3 : 0] b__h139282, b__h3158; + wire [2 : 0] n__read_id__h64100, n__read_id__h64185; wire [1 : 0] IF_enqDst_0_lat_0_whas__263_THEN_enqDst_0_lat__ETC___d1415, IF_enqDst_0_lat_0_whas__263_THEN_enqDst_0_lat__ETC___d1426, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1560, @@ -2174,22 +2174,22 @@ module mkProc(CLK, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d452, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d474, mmioPlatform_mtip_0_18_OR_NOT_mmioPlatform_mti_ETC___d524, - mmioPlatform_reqBE_BIT_0___h30068, - mmioPlatform_reqBE_BIT_4___h30028, + mmioPlatform_reqBE_BIT_0___h30085, + mmioPlatform_reqBE_BIT_4___h30045, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d593, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d702, mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d775, mmioPlatform_toHostQ_enqReq_dummy2_2_read__04__ETC___d216, - n__read_child__h64085, - n__read_child__h64170, - n__read_child__h83004, - n__read_child__h83083, - n__read_snd_id__h98574, + n__read_child__h64101, + n__read_child__h64186, + n__read_child__h83020, + n__read_child__h83099, + n__read_snd_id__h98590, propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361, propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365, - x__h63898, - x__h77752, - x__h82823; + x__h63914, + x__h77768, + x__h82839; // action method hart0_server_reset_request_put assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -3362,13 +3362,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h3144 == 4'd0 ; + b__h3158 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h3144 != 4'd0 && + b__h3158 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3480,7 +3480,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h43972 == 64'd0 || + x__h43988 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3657,13 +3657,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h139266 == 4'd0 ; + b__h139282 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h139266 != 4'd0 && + b__h139282 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3671,8 +3671,8 @@ module mkProc(CLK, CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = WILL_FIRE_RL_rl_reset ; - assign WILL_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; + assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = @@ -3755,7 +3755,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h30443 } ; + x_data__h30460 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 && @@ -3790,7 +3790,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__85__ETC___d1216 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31864 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31881 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3897,7 +3897,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h50193 } ; + x__h50209 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_ETC___d608, @@ -3906,52 +3906,52 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h52305, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h52321, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { 1'd1, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43972 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h43988 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h43972 != 64'd0 ; + x__h43988 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41906 == 64'd0 ; + x__h41922 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898 ; + x__h63914 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15, + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823 ; + x__h82839 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26, + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732 } ; assign enqDst_0_lat_0_1$wget = - { 1'd1, n__read_snd_addr__h98573, n__read_snd_id__h98574 } ; + { 1'd1, n__read_snd_addr__h98589, n__read_snd_id__h98590 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -4000,13 +4000,13 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h3144 - 4'd1 ; + b__h3158 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h3144 ; + b__h3158 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - WILL_FIRE_RL_rl_reset ? + CAN_FIRE_RL_rl_reset ? 4'd0 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = @@ -4057,13 +4057,13 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h139266 - 4'd1 ; + b__h139282 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h139266 ; + b__h139282 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = - WILL_FIRE_RL_rl_reset ? + CAN_FIRE_RL_rl_reset ? 4'd0 : llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ; @@ -4139,7 +4139,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h139558, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h139574, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -4150,13 +4150,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h153482, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h153498, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h153397, strb8__h153398, 1'd1 } ; + { 4'd0, data64__h153413, strb8__h153414, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4168,7 +4168,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h140260 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h140276 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4305,7 +4305,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h35396 : + newData__h35413 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4314,7 +4314,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h31946 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h31963 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4744,7 +4744,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h136445, llc$dma_respLd_first[3] } ; + { ld_data__h136461, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4890,11 +4890,11 @@ module mkProc(CLK, // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = WILL_FIRE_RL_rl_reset ; + assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = WILL_FIRE_RL_rl_reset ; + assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -4935,7 +4935,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1581 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h140260, + { new_cline__h140276, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5196,54 +5196,54 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), - .amoExec_current_data(value__h38933), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h32057)); + .amoExec_current_data(value__h38950), + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h32074)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h37701), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h35487)); + .amoExec_current_data(mmioPlatform_mtime__h37718), + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h35504)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h43716), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h41917)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h43732), + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h41933)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h30028 && - mmioPlatform_reqBE_BIT_0___h30068, + mmioPlatform_reqBE_BIT_4___h30045 && + mmioPlatform_reqBE_BIT_0___h30085, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h50789), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30028 && - !mmioPlatform_reqBE_BIT_0___h30068), - .amoExec(x__h43983)); + .amoExec_in_data(mmioPlatform_reqData__h50805), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h30045 && + !mmioPlatform_reqBE_BIT_0___h30085), + .amoExec(x__h43999)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_66_BIT_ETC___d831 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h41372 } } ; + x1_avValue_data__h41388 } } ; assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_66_BIT_ETC___d879 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { IF_mmioPlatform_fromHostQ_empty_00_THEN_IF_NOT_ETC___d873, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h45993 } } ; + x1_avValue_data__h46009 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4__ETC___d690 = (IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 && !mmioPlatform_mtip_0 || @@ -5255,7 +5255,7 @@ module mkProc(CLK, (!core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) ? 67'h3AAAAAAAAAAAAAAAA : - ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd4200447) ? + ((core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : IF_core_0_mmioToPlatform_cRq_first__41_BITS_14_ETC___d364) ; assign IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d582 = @@ -5266,7 +5266,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67__ETC___d685 = - newData__h31946 <= mmioPlatform_mtime ; + newData__h31963 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__287_288_OR__ETC___d1322 = NOT_propDstIdx_0_dummy2_1_read__287_288_OR_IF__ETC___d1321 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5345,7 +5345,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1575, - x__h77752 } ; + x__h77768 } ; assign IF_enqDst_1_0_lat_1_whas__537_THEN_enqDst_1_0__ETC___d1584 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5368,8 +5368,8 @@ module mkProc(CLK, SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1211 ; assign IF_mmioPlatform_fromHostQ_empty_00_THEN_IF_NOT_ETC___d873 = mmioPlatform_fromHostQ_empty ? - x__h43972 == 64'd0 : - x__h41906 == 64'd0 ; + x__h43988 == 64'd0 : + x__h41922 == 64'd0 ; assign IF_mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioP_ETC___d764 = ((mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d755 && !mmioPlatform_mtip_0) ? @@ -5498,8 +5498,8 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_2_ETC___d891 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h43972 != 64'd0 : - x__h41906 != 64'd0) : + x__h43988 != 64'd0 : + x__h41922 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__54__ETC___d163 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? @@ -5745,49 +5745,49 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__325_TH_ETC___d1389 = - { CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14, + { CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13, + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__640__ETC___d1732 = - { CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725, - x__h85239 } ; + x__h85255 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674 = - { CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1674, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1691, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1725 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__464_THE_ETC___d1708, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__325_AND_I_ETC___d1388 = - { CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12, - x__h64212, - x__h64219 } ; - assign b__h139266 = + { CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12, + x__h64228, + x__h64235 } ; + assign b__h139282 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h3144 = + assign b__h3158 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d343 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194304 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554432 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194305 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4196352 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33556480 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350 = - core_0$mmioToPlatform_cRq_first[141:81] < 61'd4196353 ; + core_0$mmioToPlatform_cRq_first[141:81] < 61'd33556481 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 = core_0$mmioToPlatform_cRq_first[141:81] == mmioPlatform_toHostAddr ; @@ -5799,24 +5799,24 @@ module mkProc(CLK, !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345) && (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] == 61'd4200447 ; + core_0$mmioToPlatform_cRq_first[141:81] == 61'd33560575 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d539 = (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d343 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345) && (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] != 61'd4200447 && + core_0$mmioToPlatform_cRq_first[141:81] != 61'd33560575 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d545 = (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] != 61'd4200447 && + core_0$mmioToPlatform_cRq_first[141:81] != 61'd33560575 && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d359 ; assign core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d552 = (core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 || !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350) && - core_0$mmioToPlatform_cRq_first[141:81] != 61'd4200447 && + core_0$mmioToPlatform_cRq_first[141:81] != 61'd33560575 && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d356 && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d359 ; assign core_0_mmioToPlatform_cRq_notEmpty__27_AND_cor_ETC___d528 = @@ -5825,22 +5825,22 @@ module mkProc(CLK, !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345) && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d348 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d350 ; - assign data__h31864 = + assign data__h31881 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h31657, 32'd0 } ; - assign failed_testnum__h168166 = + { v__h31674, 32'd0 } ; + assign failed_testnum__h168182 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign lower_data__h31801 = - mmioPlatform_waitLowerMSIPCRs ? v__h31694 : 32'd0 ; - assign mem_req_rd_addr_araddr__h139558 = - { llc$to_mem_toM_first[68:11], x__h139593 } ; - assign mem_req_wr_addr_awaddr__h153482 = - { llc$to_mem_toM_first[639:582], x__h153507 } ; + assign lower_data__h31818 = + mmioPlatform_waitLowerMSIPCRs ? v__h31711 : 32'd0 ; + assign mem_req_rd_addr_araddr__h139574 = + { llc$to_mem_toM_first[68:11], x__h139609 } ; + assign mem_req_wr_addr_awaddr__h153498 = + { llc$to_mem_toM_first[639:582], x__h153523 } ; assign mmioPlatform_cycle_10_ULT_99___d311 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_195_ULT_mmioPlatform__ETC___d1204 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h43716 = + assign mmioPlatform_fromHostQ_data_0__h43732 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d294 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -5851,9 +5851,9 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h37701 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h37718 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d755 = - mmioPlatform_mtimecmp_0 <= newData__h35396 ; + mmioPlatform_mtimecmp_0 <= newData__h35413 ; assign mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = @@ -5954,9 +5954,9 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_notEmpty && !core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d343 && core_0_mmioToPlatform_cRq_first__41_BITS_141_T_ETC___d345 ; - assign mmioPlatform_reqBE_BIT_0___h30068 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h30028 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h50789 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h30085 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h30045 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h50805 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ_0_68_ETC___d593 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -5983,104 +5983,104 @@ module mkProc(CLK, !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h64080 = + assign n__read_addr__h64096 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h64165 = + assign n__read_addr__h64181 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h83001 = + assign n__read_addr__h83017 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1469 : 64'd0 ; - assign n__read_addr__h83080 = + assign n__read_addr__h83096 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1507 : 64'd0 ; - assign n__read_child__h64085 = + assign n__read_child__h64101 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h64170 = + assign n__read_child__h64186 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h83004 = + assign n__read_child__h83020 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1495 ; - assign n__read_child__h83083 = + assign n__read_child__h83099 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1533 ; - assign n__read_id__h64084 = + assign n__read_id__h64100 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h64169 = + assign n__read_id__h64185 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h98573 = + assign n__read_snd_addr__h98589 = propDstData_0_dummy2_1_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[64:1] : propDstData_0_rl_1[64:1]) : 64'd0 ; - assign n__read_snd_id__h98574 = + assign n__read_snd_id__h98590 = propDstData_0_dummy2_1_1$Q_OUT && (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[0] : propDstData_0_rl_1[0]) ; - assign newData__h31946 = + assign newData__h31963 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32057 : + x__h32074 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d683 ; - assign newData__h35396 = + assign newData__h35413 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h35487 : + x__h35504 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d753 ; - assign new_cline__h140260 = + assign new_cline__h140276 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h50805 = + assign op_result__h50821 = IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 + IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ; - assign op_result__h51335 = w1__h50202 ^ w2__h50204 ; - assign op_result__h51340 = w1__h50202 & w2__h50204 ; - assign op_result__h51345 = w1__h50202 | w2__h50204 ; - assign op_result__h51350 = - (w1__h50202 < w2__h50204) ? w1__h50202 : w2__h50204 ; - assign op_result__h51356 = - (w1__h50202 <= w2__h50204) ? w2__h50204 : w1__h50202 ; - assign op_result__h51363 = + assign op_result__h51351 = w1__h50218 ^ w2__h50220 ; + assign op_result__h51356 = w1__h50218 & w2__h50220 ; + assign op_result__h51361 = w1__h50218 | w2__h50220 ; + assign op_result__h51366 = + (w1__h50218 < w2__h50220) ? w1__h50218 : w2__h50220 ; + assign op_result__h51372 = + (w1__h50218 <= w2__h50220) ? w2__h50220 : w1__h50218 ; + assign op_result__h51379 = ((IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ^ 64'h8000000000000000)) ? - w1__h50202 : - w2__h50204 ; - assign op_result__h51369 = + w1__h50218 : + w2__h50220 ; + assign op_result__h51385 = ((IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 ^ 64'h8000000000000000)) ? - w2__h50204 : - w1__h50202 ; + w2__h50220 : + w1__h50218 ; assign propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -6091,130 +6091,130 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h50248 = + assign result__h50264 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0] } ; - assign result__h50372 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h50400 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h50428 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h50456 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h50484 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h50512 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h50540 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h50568 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h50613 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h50641 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h50669 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h50697 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h50738 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h50766 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h50892 = + assign result__h50388 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h50416 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h50444 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h50472 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h50500 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h50528 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h50556 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h50584 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h50629 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h50657 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h50685 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h50713 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h50754 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h50782 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h50908 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h50919 = + assign result__h50935 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h50946 = + assign result__h50962 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h50973 = + assign result__h50989 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h51000 = + assign result__h51016 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h51027 = + assign result__h51043 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h51054 = + assign result__h51070 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h51081 = + assign result__h51097 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h51125 = + assign result__h51141 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h51152 = + assign result__h51168 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h51179 = + assign result__h51195 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h51206 = + assign result__h51222 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h51246 = + assign result__h51262 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h51273 = + assign result__h51289 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h51390 = + assign result__h51406 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h51456 = + assign result__h51472 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h51522 = + assign result__h51538 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h51588 = + assign result__h51604 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h51654 = + assign result__h51670 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h51720 = + assign result__h51736 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h51786 = + assign result__h51802 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h51848 = + assign result__h51864 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0] } ; - assign result__h51893 = + assign result__h51909 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h51959 = + assign result__h51975 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h52025 = + assign result__h52041 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h52083 = + assign result__h52099 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[31:0] } ; - assign result__h52128 = + assign result__h52144 = { IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145[31:0], mmioPlatform_reqData[31:0] } ; - assign upper_data__h31802 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h31657 ; - assign v__h31657 = mmioPlatform_waitUpperMSIPCRs ? v__h31694 : 32'd0 ; - assign v__h31694 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign value__h38933 = mmioPlatform_mtimecmp_0 ; - assign w10197_BITS_31_TO_0__q7 = w1__h50197[31:0] ; - assign w1___1__h50307 = { 32'd0, w1__h50197[31:0] } ; - assign w20198_BITS_31_TO_0__q8 = w2__h50198[31:0] ; - assign w2___1__h50308 = { 32'd0, w2__h50198[31:0] } ; - assign x1_avValue_data__h41372 = x1_avValue_data__h41382 ; - assign x1_avValue_data__h41382 = + assign upper_data__h31819 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h31674 ; + assign v__h31674 = mmioPlatform_waitUpperMSIPCRs ? v__h31711 : 32'd0 ; + assign v__h31711 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign value__h38950 = mmioPlatform_mtimecmp_0 ; + assign w10213_BITS_31_TO_0__q7 = w1__h50213[31:0] ; + assign w1___1__h50323 = { 32'd0, w1__h50213[31:0] } ; + assign w20214_BITS_31_TO_0__q8 = w2__h50214[31:0] ; + assign w2___1__h50324 = { 32'd0, w2__h50214[31:0] } ; + assign x1_avValue_data__h41388 = x1_avValue_data__h41398 ; + assign x1_avValue_data__h41398 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h45993 = x1_avValue_data__h46003 ; - assign x1_avValue_data__h46003 = + assign x1_avValue_data__h46009 = x1_avValue_data__h46019 ; + assign x1_avValue_data__h46019 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h139593 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h153507 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h41906 = + assign x__h139609 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h153523 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h41922 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h41917 : + x__h41933 : IF_mmioPlatform_reqBE_69_BIT_7_50_THEN_mmioPla_ETC___d870 ; - assign x__h43972 = + assign x__h43988 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h43983 : + x__h43999 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -6223,123 +6223,123 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h52305 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h63898 = + assign x__h52321 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h63914 = SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_IF_ETC___d1318 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__287_288_OR_IF__ETC___d1321 ; - assign x__h77752 = + assign x__h77768 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__540_THEN_enqDst_1_0__ETC___d1581 ; - assign x__h82823 = + assign x__h82839 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_AND__ETC___d1633 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__592_593_OR_I_ETC___d1636 ; - assign x_data__h30443 = { 31'd0, mmioPlatform_reqData[0] } ; + assign x_data__h30460 = { 31'd0, mmioPlatform_reqData[0] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h136445 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h136445 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h136445 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h136445 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h136445 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h136445 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h136445 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h136445 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h136461 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h136461 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h136461 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h136461 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h136461 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h136461 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h136461 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h136461 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h153397 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h153397 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h153397 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h153397 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h153397 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h153397 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h153397 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h153397 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h153413 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h153413 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h153413 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h153413 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h153413 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h153413 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h153413 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h153413 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h153398 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h153398 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h153398 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h153398 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h153398 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h153398 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h153398 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h153398 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h153414 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h153414 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h153414 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h153414 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h153414 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h153414 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h153414 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h153414 = llc$to_mem_toM_first[575:568]; endcase end always@(mmioPlatform_curReq or - result__h50613 or - result__h50641 or result__h50669 or result__h50697) + result__h50388 or + result__h50416 or + result__h50444 or + result__h50472 or + result__h50500 or + result__h50528 or result__h50556 or result__h50584) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50388; + 3'h1: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50416; + 3'h2: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50444; + 3'h3: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50472; + 3'h4: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50500; + 3'h5: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50528; + 3'h6: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50556; + 3'h7: + IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = + result__h50584; + endcase + end + always@(mmioPlatform_curReq or + result__h50629 or + result__h50657 or result__h50685 or result__h50713) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50613; + result__h50629; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50641; + result__h50657; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50669; + result__h50685; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = - result__h50697; + result__h50713; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 = 64'd0; endcase end - always@(mmioPlatform_curReq or - result__h50372 or - result__h50400 or - result__h50428 or - result__h50456 or - result__h50484 or - result__h50512 or result__h50540 or result__h50568) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50372; - 3'h1: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50400; - 3'h2: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50428; - 3'h3: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50456; - 3'h4: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50484; - 3'h5: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50512; - 3'h6: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50540; - 3'h7: - IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 = - result__h50568; - endcase - end - always@(mmioPlatform_curReq or result__h50738 or result__h50766) + always@(mmioPlatform_curReq or result__h50754 or result__h50782) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h50738; + result__h50754; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h50766; + result__h50782; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -6351,102 +6351,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h50198 = + w2__h50214 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035; 2'b01: - w2__h50198 = + w2__h50214 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; 2'b10: - w2__h50198 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h50214 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h50198 = + w2__h50214 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 or - w2___1__h50308 or + w2___1__h50324 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055) begin case (mmioPlatform_reqSz) 2'b0: - w2__h50204 = + w2__h50220 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035; 2'b01: - w2__h50204 = + w2__h50220 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; - 2'b10: w2__h50204 = w2___1__h50308; + 2'b10: w2__h50220 = w2___1__h50324; 2'b11: - w2__h50204 = + w2__h50220 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_curReq or - result__h51125 or - result__h51152 or result__h51179 or result__h51206) + result__h51141 or + result__h51168 or result__h51195 or result__h51222) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51125; + result__h51141; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51152; + result__h51168; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51179; + result__h51195; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = - result__h51206; + result__h51222; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h50892 or - result__h50919 or - result__h50946 or - result__h50973 or - result__h51000 or - result__h51027 or result__h51054 or result__h51081) + result__h50908 or + result__h50935 or + result__h50962 or + result__h50989 or + result__h51016 or + result__h51043 or result__h51070 or result__h51097) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50892; + result__h50908; 3'h1: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50919; + result__h50935; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50946; + result__h50962; 3'h3: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h50973; + result__h50989; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51000; + result__h51016; 3'h5: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51027; + result__h51043; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51054; + result__h51070; 3'h7: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 = - result__h51081; + result__h51097; endcase end - always@(mmioPlatform_curReq or result__h51246 or result__h51273) + always@(mmioPlatform_curReq or result__h51262 or result__h51289) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h51246; + result__h51262; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h51273; + result__h51289; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -6458,41 +6458,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h50197 = + w1__h50213 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087; 2'b01: - w1__h50197 = + w1__h50213 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; 2'b10: - w1__h50197 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h50213 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h50197 = + w1__h50213 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 or - w1___1__h50307 or + w1___1__h50323 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106) begin case (mmioPlatform_reqSz) 2'b0: - w1__h50202 = + w1__h50218 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087; 2'b01: - w1__h50202 = + w1__h50218 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; - 2'b10: w1__h50202 = w1___1__h50307; + 2'b10: w1__h50218 = w1___1__h50323; 2'b11: - w1__h50202 = + w1__h50218 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1087 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099 or - w10197_BITS_31_TO_0__q7 or + w10213_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106) begin case (mmioPlatform_reqSz) @@ -6504,7 +6504,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1099; 2'b10: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 = - { {32{w10197_BITS_31_TO_0__q7[31]}}, w10197_BITS_31_TO_0__q7 }; + { {32{w10213_BITS_31_TO_0__q7[31]}}, w10213_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1113 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1106; @@ -6513,7 +6513,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1035 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048 or - w20198_BITS_31_TO_0__q8 or + w20214_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055) begin case (mmioPlatform_reqSz) @@ -6525,115 +6525,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1048; 2'b10: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 = - { {32{w20198_BITS_31_TO_0__q8[31]}}, w20198_BITS_31_TO_0__q8 }; + { {32{w20214_BITS_31_TO_0__q8[31]}}, w20214_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_005_EQ_0b10_012_THEN_SEX_ETC___d1115 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h51369 or - w2__h50204 or - op_result__h50805 or - op_result__h51335 or - op_result__h51340 or - op_result__h51345 or - op_result__h51363 or op_result__h51350 or op_result__h51356) + op_result__h51385 or + w2__h50220 or + op_result__h50821 or + op_result__h51351 or + op_result__h51356 or + op_result__h51361 or + op_result__h51379 or op_result__h51366 or op_result__h51372) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - w2__h50204; + w2__h50220; 4'd1: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h50805; + op_result__h50821; 4'd2: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51335; + op_result__h51351; 4'd3: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51340; + op_result__h51356; 4'd4: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51345; + op_result__h51361; 4'd5: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51363; + op_result__h51379; 4'd7: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51350; + op_result__h51366; 4'd8: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51356; + op_result__h51372; default: IF_mmioPlatform_reqAmofunc_010_EQ_0_011_THEN_I_ETC___d1145 = - op_result__h51369; + op_result__h51385; endcase end always@(mmioPlatform_curReq or - result__h51848 or - result__h51893 or result__h51959 or result__h52025) + result__h51864 or + result__h51909 or result__h51975 or result__h52041) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51848; + result__h51864; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51893; + result__h51909; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h51959; + result__h51975; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = - result__h52025; + result__h52041; default: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h50248 or - result__h51390 or - result__h51456 or - result__h51522 or - result__h51588 or - result__h51654 or result__h51720 or result__h51786) + result__h50264 or + result__h51406 or + result__h51472 or + result__h51538 or + result__h51604 or + result__h51670 or result__h51736 or result__h51802) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h50248; + result__h50264; 3'h1: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51390; + result__h51406; 3'h2: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51456; + result__h51472; 3'h3: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51522; + result__h51538; 3'h4: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51588; + result__h51604; 3'h5: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51654; + result__h51670; 3'h6: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51720; + result__h51736; 3'h7: IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169 = - result__h51786; + result__h51802; endcase end - always@(mmioPlatform_curReq or result__h52083 or result__h52128) + always@(mmioPlatform_curReq or result__h52099 or result__h52144) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h52083; + result__h52099; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h52128; + result__h52144; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -6645,15 +6645,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h50193 = + x__h50209 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1169; 2'b01: - x__h50193 = + x__h50209 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1178; 2'b10: - x__h50193 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h50209 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h50193 = + x__h50209 = IF_mmioPlatform_curReq_61_BITS_2_TO_0_007_EQ_0_ETC___d1055; endcase end @@ -6737,278 +6737,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__456_THEN_propDst_ETC___d1459; endcase end - always@(x__h63898 or n__read_id__h64084 or n__read_id__h64169) + always@(x__h63914 or n__read_id__h64100 or n__read_id__h64185) begin - case (x__h63898) - 1'd0: x__h64212 = n__read_id__h64084; - 1'd1: x__h64212 = n__read_id__h64169; + case (x__h63914) + 1'd0: x__h64228 = n__read_id__h64100; + 1'd1: x__h64228 = n__read_id__h64185; endcase end - always@(x__h63898 or n__read_child__h64085 or n__read_child__h64170) + always@(x__h63914 or n__read_child__h64101 or n__read_child__h64186) begin - case (x__h63898) - 1'd0: x__h64219 = n__read_child__h64085; - 1'd1: x__h64219 = n__read_child__h64170; + case (x__h63914) + 1'd0: x__h64235 = n__read_child__h64101; + 1'd1: x__h64235 = n__read_child__h64186; endcase end - always@(x__h63898 or + always@(x__h63914 or propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361 or propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12 = + CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12 = propDstData_0_dummy2_1_read__325_AND_IF_propDs_ETC___d1361; 1'd1: - CASE_x3898_0_propDstData_0_dummy2_1_read__325__ETC__q12 = + CASE_x3914_0_propDstData_0_dummy2_1_read__325__ETC__q12 = propDstData_1_dummy2_1_read__330_AND_IF_propDs_ETC___d1365; endcase end - always@(x__h63898 or + always@(x__h63914 or IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1341 or IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1345) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1341; 1'd1: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q13 = IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1345; endcase end - always@(x__h63898 or + always@(x__h63914 or IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1351 or IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1355) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = IF_propDstData_0_dummy2_1_read__325_THEN_IF_pr_ETC___d1351; 1'd1: - CASE_x3898_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = + CASE_x3914_0_IF_propDstData_0_dummy2_1_read__3_ETC__q14 = IF_propDstData_1_dummy2_1_read__330_THEN_IF_pr_ETC___d1355; endcase end - always@(x__h63898 or n__read_addr__h64080 or n__read_addr__h64165) + always@(x__h63914 or n__read_addr__h64096 or n__read_addr__h64181) begin - case (x__h63898) + case (x__h63914) 1'd0: - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15 = - n__read_addr__h64080; + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15 = + n__read_addr__h64096; 1'd1: - CASE_x3898_0_n__read_addr4080_1_n__read_addr41_ETC__q15 = - n__read_addr__h64165; + CASE_x3914_0_n__read_addr4096_1_n__read_addr41_ETC__q15 = + n__read_addr__h64181; endcase end - always@(x__h82823 or n__read_child__h83004 or n__read_child__h83083) + always@(x__h82839 or n__read_child__h83020 or n__read_child__h83099) begin - case (x__h82823) - 1'd0: x__h85239 = n__read_child__h83004; - 1'd1: x__h85239 = n__read_child__h83083; + case (x__h82839) + 1'd0: x__h85255 = n__read_child__h83020; + 1'd1: x__h85255 = n__read_child__h83099; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h82823 or + always@(x__h82839 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x2823_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x2839_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h82823 or + always@(x__h82839 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1474 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1512) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__464_THEN_propDs_ETC___d1474 : 2'd0; 1'd1: - CASE_x2823_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x2839_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__502_THEN_propDs_ETC___d1512 : 2'd0; endcase end - always@(x__h82823 or + always@(x__h82839 or NOT_propDstData_1_0_dummy2_1_read__640_651_OR__ETC___d1652 or NOT_propDstData_1_1_dummy2_1_read__642_653_OR__ETC___d1654) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__640_651_OR__ETC___d1652; 1'd1: - CASE_x2823_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x2839_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__642_653_OR__ETC___d1654; endcase end - always@(x__h82823 or n__read_addr__h83001 or n__read_addr__h83080) + always@(x__h82839 or n__read_addr__h83017 or n__read_addr__h83096) begin - case (x__h82823) + case (x__h82839) 1'd0: - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26 = - n__read_addr__h83001; + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26 = + n__read_addr__h83017; 1'd1: - CASE_x2823_0_n__read_addr3001_1_n__read_addr30_ETC__q26 = - n__read_addr__h83080; + CASE_x2839_0_n__read_addr3017_1_n__read_addr30_ETC__q26 = + n__read_addr__h83096; endcase end @@ -7418,13 +7418,13 @@ module mkProc(CLK, if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394) begin - v__h64898 = $time; + v__h64914 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394) - $display("%t XBar %m: deq src %d", v__h64898, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h64914, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__287_AND_ETC___d1394 && @@ -7432,30 +7432,30 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898) + x__h63914) begin - v__h65518 = $time; + v__h65534 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898) - $display("%t XBar %m: deq src %d", v__h65518, $signed(32'd1)); + x__h63914) + $display("%t XBar %m: deq src %d", v__h65534, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_read__308_309_OR_NOT_enq_ETC___d1324 && - x__h63898 && + x__h63914 && (!propDstIdx_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) begin - v__h66335 = $time; + v__h66351 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) - $write("%t XBAR %m: enq dst %d ; ", v__h66335, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h66351, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq) $write("CRqMsg { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) @@ -7544,13 +7544,13 @@ module mkProc(CLK, if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737) begin - v__h85916 = $time; + v__h85932 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737) - $display("%t XBar %m: deq src %d", v__h85916, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h85932, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__592_A_ETC___d1737 && @@ -7558,30 +7558,30 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823) + x__h82839) begin - v__h86536 = $time; + v__h86552 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823) - $display("%t XBar %m: deq src %d", v__h86536, $signed(32'd1)); + x__h82839) + $display("%t XBar %m: deq src %d", v__h86552, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_1_0_dummy2_0_read__623_624_OR_NOT_e_ETC___d1639 && - x__h82823 && + x__h82839 && (!propDstIdx_1_1_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) begin - v__h88783 = $time; + v__h88799 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) - $write("%t XBAR %m: enq dst %d ; ", v__h88783, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h88799, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_1) $write("CRsMsg { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) @@ -7751,12 +7751,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875) begin - v__h99220 = $time; + v__h99236 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875) - $display("%t XBar %m: deq src %d", v__h99220, $signed(32'd0)); + $display("%t XBar %m: deq src %d", v__h99236, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (NOT_enqDst_0_dummy2_0_1_read__868_869_OR_NOT_e_ETC___d1875 && !CAN_FIRE_RL_srcPropose_4 && @@ -7765,12 +7765,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) begin - v__h99988 = $time; + v__h100004 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) - $write("%t XBAR %m: enq dst %d ; ", v__h99988, $signed(32'd0)); + $write("%t XBAR %m: enq dst %d ; ", v__h100004, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) $write("<"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_doEnq_2) $write("'h%h", 1'd0); @@ -8117,7 +8117,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sendLdRespToTlb) $write("TlbLdResp { ", "data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sendLdRespToTlb) $write("'h%h", ld_data__h136445); + if (WILL_FIRE_RL_sendLdRespToTlb) $write("'h%h", ld_data__h136461); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sendLdRespToTlb) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) @@ -8183,7 +8183,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h168166); + $display("FAIL %0d", failed_testnum__h168182); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8191,14 +8191,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4974 = $stime; + v__h4988 = $stime; #0; end - v__h4968 = v__h4974 / 32'd10; + v__h4982 = v__h4988 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4968); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4982); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8257,15 +8257,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h5140 = $stime; + v__h5154 = $stime; #0; end - v__h5134 = v__h5140 / 32'd10; + v__h5148 = v__h5154 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h5134); + v__h5148); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -8354,15 +8354,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h5418 = $stime; + v__h5432 = $stime; #0; end - v__h5412 = v__h5418 / 32'd10; + v__h5426 = v__h5432 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h5412); + v__h5426); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8531,14 +8531,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h7457 = $stime; + v__h7471 = $stime; #0; end - v__h7451 = v__h7457 / 32'd10; + v__h7465 = v__h7471 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h7451); + $display("%0d: ERROR: CreditCounter: overflow", v__h7465); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -8691,15 +8691,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h3250 = $stime; + v__h3264 = $stime; #0; end - v__h3244 = v__h3250 / 32'd10; + v__h3258 = v__h3264 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h3244); + v__h3258); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -8964,14 +8964,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h7758 = $stime; + v__h7772 = $stime; #0; end - v__h7752 = v__h7758 / 32'd10; + v__h7766 = v__h7772 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h7752); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h7766); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9008,15 +9008,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h8249 = $stime; + v__h8263 = $stime; #0; end - v__h8243 = v__h8249 / 32'd10; + v__h8257 = v__h8263 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h8243); + v__h8257); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -9056,14 +9056,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h8412 = $stime; + v__h8426 = $stime; #0; end - v__h8406 = v__h8412 / 32'd10; + v__h8420 = v__h8426 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h8406); + v__h8420); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -9749,8 +9749,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h31801, - upper_data__h31802); + lower_data__h31818, + upper_data__h31819); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -9817,7 +9817,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d720) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h31946, "\n"); + $write(", new mtimecmp[%d] %x", 1'd0, newData__h31963, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -9897,7 +9897,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d791) - $write(", new mtime %x", newData__h35396, ", mtimecmp "); + $write(", new mtime %x", newData__h35413, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && NOT_mmioPlatform_reqFunc_66_BITS_5_TO_4_67_EQ__ETC___d791) @@ -9995,7 +9995,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) - $write("'h%h", x1_avValue_data__h41382, " }"); + $write("'h%h", x1_avValue_data__h41398, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) @@ -10008,13 +10008,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h43972 != 64'd0) + x__h43988 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h41906 != 64'd0) + x__h41922 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -10049,7 +10049,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) - $write("'h%h", x1_avValue_data__h46003, " }"); + $write("'h%h", x1_avValue_data__h46019, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) @@ -10357,7 +10357,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", x__h52305); + $write("'h%h", x__h52321); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -10478,15 +10478,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) begin - v__h139957 = $stime; + v__h139973 = $stime; #0; end - v__h139951 = v__h139957 / 32'd10; + v__h139967 = v__h139973 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h139951, + v__h139967, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -10546,15 +10546,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h140124 = $stime; + v__h140140 = $stime; #0; end - v__h140118 = v__h140124 / 32'd10; + v__h140134 = v__h140140 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h140118); + v__h140134); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -10735,16 +10735,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h142227 = $stime; + v__h142243 = $stime; #0; end - v__h142221 = v__h142227 / 32'd10; + v__h142237 = v__h142243 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h142221); + v__h142237); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -11942,14 +11942,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h159573 = $stime; + v__h159589 = $stime; #0; end - v__h159567 = v__h159573 / 32'd10; + v__h159583 = v__h159589 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h159567); + $display("%0d: ERROR: CreditCounter: overflow", v__h159583); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -11973,7 +11973,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", mem_req_wr_addr_awaddr__h153482); + $write("'h%h", mem_req_wr_addr_awaddr__h153498); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12069,7 +12069,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", data64__h153397); + $write("'h%h", data64__h153413); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12077,7 +12077,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", strb8__h153398); + $write("'h%h", strb8__h153414); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12103,16 +12103,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h139339 = $stime; + v__h139355 = $stime; #0; end - v__h139333 = v__h139339 / 32'd10; + v__h139349 = v__h139355 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h139333, + v__h139349, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -12200,7 +12200,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) - $write("'h%h", mem_req_rd_addr_araddr__h139558); + $write("'h%h", mem_req_rd_addr_araddr__h139574); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) @@ -12281,15 +12281,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) begin - v__h166268 = $stime; + v__h166284 = $stime; #0; end - v__h166262 = v__h166268 / 32'd10; + v__h166278 = v__h166284 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__967_U_ETC___d1984) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h166262, + v__h166278, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -12327,15 +12327,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h166776 = $stime; + v__h166792 = $stime; #0; end - v__h166770 = v__h166776 / 32'd10; + v__h166786 = v__h166792 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h166770); + v__h166786); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_Testbench/SoC/SoC_Map.bsv b/src_Testbench/SoC/SoC_Map.bsv index a6d7216..f254115 100644 --- a/src_Testbench/SoC/SoC_Map.bsv +++ b/src_Testbench/SoC/SoC_Map.bsv @@ -22,9 +22,9 @@ package SoC_Map; // ================================================================ // Exports -export SoC_Map_IFC (..), mkSoC_Map; +export SoC_Map_Struct (..), soc_map_struct; -// export fn_addr_in_range; +export SoC_Map_IFC (..), mkSoC_Map; export Num_Masters; export imem_master_num; @@ -49,6 +49,36 @@ export irq_num_uart0; import Fabric_Defs :: *; // Only for type Fabric_Addr +// ================================================================ +// Top-level-struct version of the SoC Map for RISCY-OOO + +typedef struct { + Bit #(64) near_mem_io_addr_base; + Bit #(64) near_mem_io_addr_size; + + Bit #(64) boot_rom_addr_base; + Bit #(64) boot_rom_addr_size; + + Bit #(64) mem0_controller_addr_base; + Bit #(64) mem0_controller_addr_size; + + Bit #(64) pc_reset_value; + } SoC_Map_Struct +deriving (FShow); + +SoC_Map_Struct soc_map_struct = +SoC_Map_Struct { + near_mem_io_addr_base: 'h_0200_0000, + + boot_rom_addr_base: 'h_0000_1000, + boot_rom_addr_size: 'h_0000_1000, + + mem0_controller_addr_base: 'h_8000_0000, + mem0_controller_addr_size: 'h_1000_0000, + + pc_reset_value: 'h_0000_1000 + }; + // ================================================================ // Interface and module for the address map diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index 894b08a..fb6e72d 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -349,6 +349,10 @@ module mkSoC_Top (SoC_Top_IFC); // For ISA tests: watch memory writes to addr method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr); mem0_controller.set_watch_tohost (watch_tohost, tohost_addr); + if (watch_tohost) begin + let fromhost_addr = 0; + corew.set_htif_addrs (tohost_addr, fromhost_addr); + end endmethod endmodule: mkSoC_Top