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Add missing module (FIFOL1) to Xilinx import.

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Darius Rad
2019-04-22 22:04:20 -04:00
parent 532998461d
commit 4fba332f17
2 changed files with 163 additions and 0 deletions
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8
src_SSITH_P3/xilinx_ip/component.xml
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@@ -2929,6 +2929,10 @@
<spirit:name>hdl/ResetEither.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/FIFOL1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:name>
@@ -3485,6 +3489,10 @@
<spirit:name>hdl/ResetEither.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/FIFOL1.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:name>