From 56885f06c054e6b554e0427ae9509581f7faa5aa Mon Sep 17 00:00:00 2001
From: jon <jonwoodruff@gmail.com>
Date: Tue, 7 Apr 2020 16:32:31 +0100
Subject: [PATCH] Changes for CJALR-only TestRIG to work. This includes
 replacing register read values with nullCap if reading x0, which is generally
 necessary. This is more-or-less using a new mechanism which shouldn't
 actually be necessary if the default value in the register file is nullCap.
 (In RVFI_DII, we initialise with the almightyCap instead.)

---
 .../RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv     | 12 ++++++------
 src_Core/RISCY_OOO/procs/lib/Exec.bsv                |  9 ++++++---
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
index d8e1228..671b719 100755
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
@@ -246,17 +246,17 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
         let regsReady = inIfc.sbCons_lazyLookup(x.regs);
 
         // get rVal1 (check bypass)
-        CapPipe rVal1 = ?;
+        CapPipe rVal1 = nullCap;
         if(x.dInst.csr matches tagged Valid .csr) begin
             rVal1 = nullWithAddr(inIfc.csrf_rd(csr));
         end
-        else if(x.regs.src1 matches tagged Valid .src1) begin
+        else if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
             rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
         end
 
         // get rVal2 (check bypass)
-        CapPipe rVal2 = ?;
-        if(x.regs.src2 matches tagged Valid .src2) begin
+        CapPipe rVal2 = nullCap;
+        if(x.regs.src2 matches tagged Valid .src2 &&& src2 != 0) begin
             rVal2 <- readRFBypass(src2, regsReady.src2, inIfc.rf_rd2(src2), bypassWire);
         end
 
@@ -288,9 +288,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
         let regToExe = regToExeQ.first;
         let x = regToExe.data;
         if(verbose) $display("[doExeAlu] ", fshow(regToExe));
-
+        CapPipe pcc = setAddrUnsafe(cast(inIfc.scaprf_rd(SCR_PCC)), x.pc);
         // execution
-        ExecResult exec_result = basicExec(x.dInst, x.rVal1, x.rVal2, x.pc, x.ppc, x.orig_inst);
+        ExecResult exec_result = basicExec(x.dInst, x.rVal1, x.rVal2, pcc, x.ppc, x.orig_inst);
 
         if (verbosity > 0) begin
            $display ("AluExePipeline.doExeAlu: regToExe    = ", fshow (regToExe));
diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv
index 4f94b92..3a581e0 100755
--- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv
@@ -207,12 +207,14 @@ function ControlFlow getControlFlow(DecodedInst dInst, Data rVal1, Data rVal2, A
 endfunction
 
 (* noinline *)
-function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, Addr pc, Addr ppc, Bit #(32) orig_inst);
+function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, CapPipe pcc, Addr ppc, Bit #(32) orig_inst);
     // just data, addr, and control flow
+    Addr pc = getAddr(pcc);
     CapPipe data = nullCap;
     Data csr_data = 0;
     CapPipe addr = nullCap;
-    ControlFlow cf = ControlFlow{pc: pc, nextPc: 0, taken: False, newPcc: dInst.capChecks.src1_tag, mispredict: False};
+    Bool cjalr = (dInst.iType == Jr) && dInst.capChecks.src1_tag;
+    ControlFlow cf = ControlFlow{pc: pc, nextPc: 0, taken: False, newPcc: cjalr, mispredict: False};
 
     CapPipe aluVal2 = rVal2;
     if (getDInstImm(dInst) matches tagged Valid .imm) aluVal2 = nullWithAddr(imm); //isValid(dInst.imm) ? fromMaybe(?, dInst.imm) : rVal2;
@@ -231,10 +233,11 @@ function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, A
     cf.mispredict = cf.nextPc != ppc;
 
     Addr fallthrough_incr = ((orig_inst [1:0] == 2'b11) ? 4 : 2);
+    CapPipe link_pcc = setAddrUnsafe(pcc, getAddr(pcc) + fallthrough_incr);
 
     data = (case (dInst.iType)
             St, Sc, Amo : rVal2;
-            J, Jr       : nullWithAddr(pc + fallthrough_incr); // could be computed with alu
+            J, Jr       : (cjalr ? link_pcc : nullWithAddr(getAddr(link_pcc))); // could be computed with alu
             Auipc       : nullWithAddr(pc + fromMaybe(?, getDInstImm(dInst))); // could be computed with alu
             Csr         : rVal1;
             CapInspect  : nullWithAddr(inspect_result);