From 59eddfbb4cb01f857c26e0c0b7e5f68b54841704 Mon Sep 17 00:00:00 2001 From: jon Date: Thu, 9 Jul 2020 10:26:08 +0100 Subject: [PATCH] Move register in reorder buffer that is only used for Tandem Verification to that case only. --- .../procs/RV64G_OOO/AluExePipeline.bsv | 4 ++ .../procs/RV64G_OOO/FpuMulDivExePipeline.bsv | 9 +++- .../RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 6 +-- .../RISCY_OOO/procs/lib/ReorderBuffer.bsv | 43 +++++++++++++++---- 4 files changed, 49 insertions(+), 13 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index b2cdc19..87ee0f2 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -169,7 +169,9 @@ interface AluExeInput; method Bit #(32) rob_getOrig_Inst (InstTag t); method Action rob_setExecuted( InstTag t, +`ifdef INCLUDE_TANDEM_VERIF CapPipe dst_data, +`endif Maybe#(Data) csrData, Maybe#(CapPipe) scrData, ControlFlow cf, @@ -385,7 +387,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); // update the instruction in the reorder buffer. inIfc.rob_setExecuted( x.tag, +`ifdef INCLUDE_TANDEM_VERIF x.data, +`endif x.csrData, x.scrData, x.controlFlow, diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv index dfef24e..1edc5f1 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv @@ -111,7 +111,9 @@ interface FpuMulDivExeInput; // ROB method Action rob_setExecuted( InstTag t, +`ifdef INCLUDE_TANDEM_VERIF Data dst_data, +`endif Bit#(5) fflags, Maybe#(Exception) cast `ifdef RVFI @@ -254,7 +256,12 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); inIfc.writeRegFile(valid_dst.indx, nullWithAddr(data)); end // update the instruction in the reorder buffer. - inIfc.rob_setExecuted(tag, data, fflags, tagged Invalid + inIfc.rob_setExecuted(tag, +`ifdef INCLUDE_TANDEM_VERIF + data, +`endif + fflags, + tagged Invalid `ifdef RVFI_DII , ExtraTraceBundle{regWriteData: data, memByteEn: ?} `endif diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 315a7f0..b6e048d 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -351,8 +351,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); orig_inst: orig_inst, iType: dInst.iType, dst: arch_regs.dst, - dst_data: ?, // Available only after execution `ifdef INCLUDE_TANDEM_VERIF + dst_data: ?, // Available only after execution store_data: ?, store_data_BE: ?, `endif @@ -552,8 +552,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); orig_inst: orig_inst, iType: dInst.iType, dst: arch_regs.dst, - dst_data: ?, // Available only after execution `ifdef INCLUDE_TANDEM_VERIF + dst_data: ?, // Available only after execution store_data: ?, store_data_BE: ?, `endif @@ -1095,8 +1095,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); orig_inst: orig_inst, iType: dInst.iType, dst: arch_regs.dst, - dst_data: ?, // Available only after execution `ifdef INCLUDE_TANDEM_VERIF + dst_data: ?, // Available only after execution store_data: ?, store_data_BE: ?, `endif diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index 1609f8d..dd56b39 100755 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -79,9 +79,9 @@ typedef struct { Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b) IType iType; Maybe#(ArchRIndx) dst; // Invalid, GPR or FPR destination ("Rd") - CapPipe dst_data; // Output of instruction into destination register `ifdef INCLUDE_TANDEM_VERIF // Store-data, for those mem instrs that store data + Data dst_data; // Output of instruction into destination register Data store_data; ByteEn store_data_BE; `endif @@ -128,7 +128,9 @@ typedef enum { interface Row_setExecuted_doFinishAlu; method Action set( +`ifdef INCLUDE_TANDEM_VERIF CapPipe dst_data, +`endif Maybe#(Data) csrData, Maybe#(CapPipe) scrData, ControlFlow cf, @@ -141,7 +143,9 @@ endinterface interface Row_setExecuted_doFinishFpuMulDiv; method Action set( +`ifdef INCLUDE_TANDEM_VERIF Data dst_data, +`endif Bit#(5) fflags, Maybe#(Exception) cause `ifdef RVFI @@ -256,8 +260,8 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p Reg #(Bit #(32)) orig_inst <- mkRegU; Reg#(IType) iType <- mkRegU; Reg #(Maybe #(ArchRIndx)) rg_dst_reg <- mkRegU; - Reg #(CapPipe) rg_dst_data <- mkRegU; `ifdef INCLUDE_TANDEM_VERIF + Reg #(Data) rg_dst_data <- mkRegU; Reg #(Data) rg_store_data <- mkRegU; Reg #(ByteEn) rg_store_data_BE <- mkRegU; `endif @@ -295,7 +299,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p for(Integer i = 0; i < valueof(aluExeNum); i = i+1) begin aluSetExe[i] = (interface Row_setExecuted_doFinishAlu; method Action set( +`ifdef INCLUDE_TANDEM_VERIF CapPipe dst_data, +`endif Maybe#(Data) csrData, Maybe#(CapPipe) scrData, ControlFlow cf, @@ -307,7 +313,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p // inst is done rob_inst_state[state_finishAlu_port(i)] <= Executed; // Destination register data, for Tandem Verification +`ifdef INCLUDE_TANDEM_VERIF rg_dst_data <= dst_data; +`endif // update PPC or csrData (vaddr is always useless for ALU results) if(csrData matches tagged Valid .d) begin @@ -335,16 +343,21 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p Vector#(fpuMulDivExeNum, Row_setExecuted_doFinishFpuMulDiv) fpuMulDivExe; for(Integer i = 0; i < valueof(fpuMulDivExeNum); i = i+1) begin fpuMulDivExe[i] = (interface Row_setExecuted_doFinishFpuMulDiv; - method Action set(Data dst_data, + method Action set( +`ifdef INCLUDE_TANDEM_VERIF + Data dst_data, +`endif Bit#(5) new_fflags, Maybe#(Exception) cause - `ifdef RVFI +`ifdef RVFI , ExtraTraceBundle tb - `endif +`endif ); // inst is done rob_inst_state[state_finishFpuMulDiv_port(i)] <= Executed; - rg_dst_data <= nullWithAddr(dst_data); +`ifdef INCLUDE_TANDEM_VERIF + rg_dst_data <= dst_data; +`endif // update fflags fflags[fflags_finishFpuMulDiv_port(i)] <= new_fflags; if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishFpuMulDiv_port(i)])) begin @@ -463,8 +476,8 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p orig_inst: orig_inst, iType: iType, dst: rg_dst_reg, - dst_data: rg_dst_data, `ifdef INCLUDE_TANDEM_VERIF + dst_data: rg_dst_data, store_data: rg_store_data, store_data_BE: rg_store_data_BE, `endif @@ -578,7 +591,9 @@ endinterface interface ROB_setExecuted_doFinishAlu; method Action set(InstTag x, - CapPipe dst_data, +`ifdef INCLUDE_TANDEM_VERIF + Data dst_data, +`endif Maybe#(Data) csrData, Maybe#(CapPipe) scrData, ControlFlow cf, @@ -591,7 +606,9 @@ endinterface interface ROB_setExecuted_doFinishFpuMulDiv; method Action set(InstTag x, +`ifdef INCLUDE_TANDEM_VERIF Data dst_data, +`endif Bit#(5) fflags, Maybe#(Exception) cause `ifdef RVFI @@ -1128,7 +1145,9 @@ module mkSupReorderBuffer#( aluSetExeIfc[i] = (interface ROB_setExecuted_doFinishAlu; method Action set( InstTag x, - CapPipe dst_data, +`ifdef INCLUDE_TANDEM_VERIF + Data dst_data, +`endif Maybe#(Data) csrData, Maybe#(CapPipe) scrData, ControlFlow cf, @@ -1140,7 +1159,9 @@ module mkSupReorderBuffer#( all(id, readVReg(setExeAlu_SB_enq)) // ordering: < enq ); row[x.way][x.ptr].setExecuted_doFinishAlu[i].set( +`ifdef INCLUDE_TANDEM_VERIF dst_data, +`endif csrData, scrData, cf, @@ -1158,7 +1179,9 @@ module mkSupReorderBuffer#( fpuMulDivSetExeIfc[i] = (interface ROB_setExecuted_doFinishFpuMulDiv; method Action set( InstTag x, +`ifdef INCLUDE_TANDEM_VERIF Data dst_data, +`endif Bit#(5) fflags, Maybe#(Exception) cause `ifdef RVFI @@ -1168,7 +1191,9 @@ module mkSupReorderBuffer#( all(id, readVReg(setExeFpuMulDiv_SB_enq)) // ordering: < enq ); row[x.way][x.ptr].setExecuted_doFinishFpuMulDiv[i].set( +`ifdef INCLUDE_TANDEM_VERIF dst_data, +`endif fflags, cause `ifdef RVFI