From 5cb283a5d5d1cd237b4514b0db75ffd3c1849e88 Mon Sep 17 00:00:00 2001
From: Karlis Susters <ks980@cam.ac.uk>
Date: Thu, 23 Feb 2023 10:30:47 +0000
Subject: [PATCH] Set up config for L1D block prefetcher

---
 builds/Resources/Include_RISCY_Config.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk
index 9960a4f..068ff52 100644
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -45,9 +45,9 @@ SIM_LLC_ARBITER_LAT ?=
 # default check cache deadlock and rename error
 CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
-INSTR_PREFETCHER_LOCATION ?= L1
+INSTR_PREFETCHER_LOCATION ?= NONE
 INSTR_PREFETCHER_TYPE ?= NEXT_LINE_ON_MISS
-DATA_PREFETCHER_LOCATION ?= NONE
+DATA_PREFETCHER_LOCATION ?= L1
 DATA_PREFETCHER_TYPE ?= BLOCK
 
 # clk frequency depends on core size