From 5e9b478371f097d91eb71d8839eebc870846c8c7 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Fri, 10 Jul 2020 10:25:53 +0100 Subject: [PATCH] Cover interesting fetch and rename state for DEBUG_WEDGE configs --- src_Core/CPU/Core.bsv | 12 +++++++ src_Core/CPU/Proc.bsv | 6 ++-- src_Core/CPU/Proc_IFC.bsv | 8 +++-- src_Core/Core/CoreW.bsv | 2 ++ src_Core/Debug_Module/Debug_Module.bsv | 34 +++++++++++++++---- .../RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 33 ++++++++++++++++++ 6 files changed, 85 insertions(+), 10 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index a282242..4b6508c 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -206,6 +206,10 @@ interface Core; method Tuple2#(CapMem, Bit#(32)) debugLastInst; (* always_enabled *) method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob; + (* always_enabled *) + method Tuple3#(Bit#(32), Addr, Addr) debugFetch; + (* always_enabled *) + method Bit#(32) debugRename; `endif endinterface @@ -1456,6 +1460,14 @@ module mkCore#(CoreId coreId)(Core); `ifdef DEBUG_WEDGE method Tuple2#(CapMem, Bit#(32)) debugLastInst = commitStage.debugLastInst; method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob = rob.debugRob; + method Tuple3#(Bit#(32), Addr, Addr) debugFetch = fetchStage.debugFetch; + method Bit#(32) debugRename; + let epochState = epochManager.getEpochState; + Bit#(8) curEp = zeroExtend(epochState.curEp); + Bit#(8) checkedEp = zeroExtend(epochState.checkedEp); + Bit#(1) pendingMMIOPRq = pack(mmio.hasPendingPRq); + return {15'b0, pendingMMIOPRq, checkedEp, curEp}; + endmethod `endif endmodule diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index c905e20..54f6852 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -334,8 +334,10 @@ module mkProc (Proc_IFC); `endif `ifdef DEBUG_WEDGE - method Tuple2#(CapMem, Bit#(32)) hart0_last_inst = core[0].debugLastInst; - method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) hart0_debug_rob = core[0].debugRob; + method Tuple2 #(CapMem, Bit #(32)) hart0_last_inst = core [0].debugLastInst; + method Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) hart0_debug_rob = core [0].debugRob; + method Tuple3 #(Bit #(32), Addr, Addr) hart0_debug_fetch = core [0].debugFetch; + method Bit #(32) hart0_debug_rename = core [0].debugRename; `endif endmodule: mkProc diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index 161a2a9..62e5ec2 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -135,9 +135,13 @@ interface Proc_IFC; `ifdef DEBUG_WEDGE (* always_enabled *) - method Tuple2#(CapMem, Bit#(32)) hart0_last_inst; + method Tuple2 #(CapMem, Bit #(32)) hart0_last_inst; (* always_enabled *) - method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) hart0_debug_rob; + method Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) hart0_debug_rob; + (* always_enabled *) + method Tuple3 #(Bit #(32), Addr, Addr) hart0_debug_fetch; + (* always_enabled *) + method Bit #(32) hart0_debug_rename; `endif endinterface diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 48d07a6..ea14bc6 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -235,6 +235,8 @@ module mkCoreW #(Reset dm_power_on_reset) `ifdef DEBUG_WEDGE mkConnection (proc.hart0_last_inst, debug_module.hart0_last_inst); mkConnection (proc.hart0_debug_rob, debug_module.hart0_debug_rob); + mkConnection (proc.hart0_debug_fetch, debug_module.hart0_debug_fetch); + mkConnection (proc.hart0_debug_rename, debug_module.hart0_debug_rename); `endif `endif diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index 6cbc582..cb96e8c 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -139,6 +139,12 @@ interface Debug_Module_IFC; (* always_enabled *) method Action hart0_debug_rob (Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) state); + + (* always_enabled *) + method Action hart0_debug_fetch (Tuple3 #(Bit #(32), Addr, Addr) state); + + (* always_enabled *) + method Action hart0_debug_rename (Bit #(32) state); `endif // ---------------- @@ -186,6 +192,12 @@ module mkDebug_Module (Debug_Module_IFC); Reg #(Bit #(32)) rg_rob_last0_inst <- mkConfigReg (0); Reg #(CapMem) rg_rob_last1_pcc <- mkConfigReg (unpack (0)); Reg #(Bit #(32)) rg_rob_last1_inst <- mkConfigReg (0); + + Reg #(Bit #(32)) rg_fetch_flags_epoch <- mkConfigReg (0); + Reg #(Addr) rg_fetch_last_itlb <- mkConfigReg (0); + Reg #(Addr) rg_fetch_last_imem <- mkConfigReg (0); + + Reg #(Bit #(32)) rg_rename_state <- mkConfigReg (0); `endif // ================================================================ @@ -305,27 +317,27 @@ module mkDebug_Module (Debug_Module_IFC); else if (dm_addr == dm_addr_custom10) - dm_word = getAddr (rg_rob_last0_pcc) [31:0]; + dm_word = rg_fetch_flags_epoch; else if (dm_addr == dm_addr_custom11) - dm_word = getAddr (rg_rob_last0_pcc) [63:32]; + dm_word = rg_fetch_last_itlb [31:0]; else if (dm_addr == dm_addr_custom12) - dm_word = rg_rob_last0_inst; + dm_word = rg_fetch_last_itlb [63:32]; else if (dm_addr == dm_addr_custom13) - dm_word = getAddr (rg_rob_last1_pcc) [31:0]; + dm_word = rg_fetch_last_imem [31:0]; else if (dm_addr == dm_addr_custom14) - dm_word = getAddr (rg_rob_last1_pcc) [63:32]; + dm_word = rg_fetch_last_imem [63:32]; else if (dm_addr == dm_addr_custom15) - dm_word = rg_rob_last1_inst; + dm_word = rg_rename_state; `endif else begin @@ -450,6 +462,16 @@ module mkDebug_Module (Debug_Module_IFC); rg_rob_last1_pcc <= tpl_3 (tpl_3 (state)); rg_rob_last1_inst <= tpl_4 (tpl_3 (state)); endmethod + + method Action hart0_debug_fetch (Tuple3 #(Bit #(32), Addr, Addr) state); + rg_fetch_flags_epoch <= tpl_1 (state); + rg_fetch_last_itlb <= tpl_2 (state); + rg_fetch_last_imem <= tpl_3 (state); + endmethod + + method Action hart0_debug_rename (Bit #(32) state); + rg_rename_state <= state; + endmethod `endif // ---------------- diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index 18ef0ad..eb7289c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -129,6 +129,10 @@ interface FetchStage; method Action lastTraceId(Dii_Id in); `endif +`ifdef DEBUG_WEDGE + method Tuple3#(Bit#(32), Addr, Addr) debugFetch; +`endif + // performance interface Perf#(DecStagePerfType) perf; endinterface @@ -510,6 +514,11 @@ module mkFetchStage(FetchStage); Reg#(Dii_Id) last_trace_id <- mkRegU; `endif +`ifdef DEBUG_WEDGE + Reg#(Addr) lastItlbReq <- mkConfigReg(0); + Reg#(Addr) lastImemReq <- mkConfigReg(0); +`endif + // Predict the next fetch-PC based only on current PC (without // knowing the instructions). @@ -584,6 +593,9 @@ module mkFetchStage(FetchStage); // Mask to 32-bit alignment, even if 'C' is supported (where we may discard first 2 bytes) Addr align32b_mask = 'h3; tlb_server.request.put (getAddr(pc) & (~ align32b_mask)); +`ifdef DEBUG_WEDGE + lastItlbReq <= getAddr(pc) & (~ align32b_mask); +`endif let out = Fetch1ToFetch2 { pc: pc, @@ -615,6 +627,9 @@ module mkFetchStage(FetchStage); MainMem: begin // Send ICache request mem_server.request.put(phys_pc); +`ifdef DEBUG_WEDGE + lastImemReq <= phys_pc; +`endif end IODevice: begin // Send MMIO req. Luckily boot rom is also aligned with @@ -624,6 +639,9 @@ module mkFetchStage(FetchStage); Bit #(TLog #(SupSize)) nbSup = truncate(nbSupX2 >> 1); mmio.bootRomReq(phys_pc, nbSup); access_mmio = True; +`ifdef DEBUG_WEDGE + lastImemReq <= phys_pc; +`endif end default: begin // Access fault @@ -633,6 +651,9 @@ module mkFetchStage(FetchStage); // tval = (in.pc & (~ align32b_mask)); Addr align16b_mask = 'h1; tval = (getAddr(in.pc) & (~ align16b_mask)); +`ifdef DEBUG_WEDGE + lastImemReq <= 'hafafafafafafafaf; +`endif end endcase end @@ -643,6 +664,9 @@ module mkFetchStage(FetchStage); // tval = (in.pc & (~ align32b_mask)); Addr align16b_mask = 'h1; tval = (getAddr(in.pc) & (~ align16b_mask)); +`ifdef DEBUG_WEDGE + lastImemReq <= 'heeeeeeeeeeeeeeee; +`endif end `endif @@ -1254,4 +1278,13 @@ module mkFetchStage(FetchStage); last_trace_id <= in; endmethod `endif + +`ifdef DEBUG_WEDGE + method Tuple3#(Bit#(32), Addr, Addr) debugFetch; + Bit#(7) flags = {pack(out_fifo.deqS[1].canDeq), pack(out_fifo.deqS[0].canDeq), pack(f32d.notEmpty), pack(f22f3.notEmpty), pack(f12f2.notEmpty), pack(waitForFlush), pack(waitForRedirect)}; + Bit #(16) epoch = zeroExtend(f_main_epoch); + Bit #(32) flagsEpoch = {8'b0, epoch, 1'b0, flags}; + return tuple3(flagsEpoch, lastItlbReq, lastImemReq); + endmethod +`endif endmodule