From 627c60b4e3946535c92df9b1306352bbd6060b76 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Thu, 9 Jul 2020 15:20:47 +0100 Subject: [PATCH] Don't generate .depends.mk if bluespec doesn't parse --- builds/Resources/Include_bluesim.mk | 2 +- builds/Resources/Include_verilator.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk index f64670f..1788e85 100644 --- a/builds/Resources/Include_bluesim.mk +++ b/builds/Resources/Include_bluesim.mk @@ -16,7 +16,7 @@ ifeq (,$(filter clean full_clean,$(MAKECMDGOALS))) include .depends.mk .depends.mk: build_dir - bluetcl -exec makedepend -elab -sim $(TMP_DIRS) $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE) + if ! bluetcl -exec makedepend -elab -sim $(TMP_DIRS) $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi endif %.bo: diff --git a/builds/Resources/Include_verilator.mk b/builds/Resources/Include_verilator.mk index f5a1237..86ff22a 100644 --- a/builds/Resources/Include_verilator.mk +++ b/builds/Resources/Include_verilator.mk @@ -19,7 +19,7 @@ ifeq (,$(filter clean full_clean,$(MAKECMDGOALS))) include .depends.mk .depends.mk: build_dir Verilog_RTL - bluetcl -exec makedepend -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE) + if ! bluetcl -exec makedepend -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi endif %.bo: