From 6509cf6445d1867f3f88ac5836a6cb2eace295d7 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Tue, 28 Feb 2023 12:29:38 +0000 Subject: [PATCH] Changed config to L1D Block-1 prefetcher and fixed potential bug --- builds/Resources/Include_RISCY_Config.mk | 4 ++-- src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk index 5c0e1c7..068ff52 100644 --- a/builds/Resources/Include_RISCY_Config.mk +++ b/builds/Resources/Include_RISCY_Config.mk @@ -45,9 +45,9 @@ SIM_LLC_ARBITER_LAT ?= # default check cache deadlock and rename error CHECK_DEADLOCK ?= true RENAME_DEBUG ?= false -INSTR_PREFETCHER_LOCATION ?= LL +INSTR_PREFETCHER_LOCATION ?= NONE INSTR_PREFETCHER_TYPE ?= NEXT_LINE_ON_MISS -DATA_PREFETCHER_LOCATION ?= NONE +DATA_PREFETCHER_LOCATION ?= L1 DATA_PREFETCHER_TYPE ?= BLOCK # clk frequency depends on core size diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index 0257561..eae2d9c 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -959,12 +959,12 @@ module mkMarkovPrefetcher(Prefetcher) provisos endmodule module mkBlockPrefetcher(Prefetcher) provisos ( - NumAlias#(numLinesEachWay, 2), + NumAlias#(numLinesEachWay, 1), Alias#(lineCountT, Bit#(TLog#(TAdd#(numLinesEachWay, 1)))) ); Reg#(Bool) nextIsForward <- mkReg(?); Reg#(LineAddr) prefetchAround <- mkReg(?); - Reg#(lineCountT) linesEachWayPrefetched <- mkReg(?); + Reg#(lineCountT) linesEachWayPrefetched <- mkReg(fromInteger(valueOf(numLinesEachWay))); method Action reportAccess(Addr addr, HitOrMiss hitMiss); if (hitMiss == MISS) begin $display("%t Prefetcher report MISS %h", $time, addr);