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Regenerate verilog

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This commit is contained in:
Jessica Clarke
2020-07-15 02:58:29 +01:00
parent 7eff218288
commit 682ff10d72
294 changed files with 298692 additions and 551876 deletions
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110
src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v
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@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Tue Jul 14 18:06:14 BST 2020
// On Wed Jul 15 02:33:07 BST 2020
//
//
// Ports:
@@ -65,7 +65,6 @@ module module_basicExec(basicExec_dInst,
reg [17 : 0] CASE_basicExec_dInst_BITS_144_TO_140_8_262143__ETC__q6;
reg [13 : 0] IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d363,
addr_capFat_addrBits__h5286;
reg [4 : 0] CASE_capChecks_13_BITS_4_TO_0_0_capChecks_13_B_ETC__q7;
reg [3 : 0] CASE_IF_basicExec_dInst_BITS_107_TO_104_4_EQ_7_ETC__q5,
CASE_basicExec_dInst_BITS_144_TO_140_2_0_4_0_5_ETC__q4,
IF_basicExec_dInst_BITS_107_TO_104_4_EQ_7_8_OR_ETC___d37,
@@ -78,7 +77,7 @@ module module_basicExec(basicExec_dInst,
addr_tempFields_repBoundTopBits__h5399;
reg [1 : 0] IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567,
addr_capFat_reserved__h5289;
reg CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q8,
reg CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q7,
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d271,
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d390,
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d403,
@@ -114,8 +113,7 @@ module module_basicExec(basicExec_dInst,
IF_basicExec_dInst_BITS_144_TO_140_EQ_15_19_TH_ETC___d636,
IF_basicExec_dInst_BITS_144_TO_140_EQ_15_19_TH_ETC___d649,
IF_basicExec_dInst_BITS_144_TO_140_EQ_15_19_TH_ETC___d664;
wire [277 : 0] NOT_basicExec_dInst_BIT_75_86_87_OR_basicExec__ETC___d984;
wire [265 : 0] prepareBoundsCheck___d977;
wire [265 : 0] prepareBoundsCheck___d929;
wire [163 : 0] capModify___d210;
wire [162 : 0] IF_basicExec_dInst_BITS_139_TO_137_49_EQ_1_50__ETC___d904,
NOT_basicExec_dInst_BIT_32_7_8_AND_IF_basicExe_ETC___d740,
@@ -346,7 +344,14 @@ module module_basicExec(basicExec_dInst,
basicExec_dInst[144:140] == 5'd11,
brAddrCalc___d258[162] != basicExec_ppc[162] ||
x__h5946 != y__h5947,
NOT_basicExec_dInst_BIT_75_86_87_OR_basicExec__ETC___d984 } ;
NOT_basicExec_dInst_BIT_75_86_87_OR_basicExec__ETC___d897 &&
(!basicExec_dInst[76] ||
_theResult___snd_capFat_address__h911[63:0] != 64'd0) &&
capChecks___d913[11],
capChecks___d913[10:0],
NOT_basicExec_dInst_BIT_75_86_87_OR_basicExec__ETC___d897 &&
prepareBoundsCheck___d929[265],
prepareBoundsCheck___d929[264:0] } ;
// remaining internal signals
module_alu instance_alu_2(.alu_a(basicExec_rVal1[159:96]),
@@ -436,7 +441,7 @@ module module_basicExec(basicExec_dInst,
.prepareBoundsCheck_vaddr(64'd0),
.prepareBoundsCheck_size(5'd0),
.prepareBoundsCheck_toCheck(basicExec_dInst_BITS_98_TO_74_05_CONCAT_IF_bas_ETC___d910),
.prepareBoundsCheck(prepareBoundsCheck___d977));
.prepareBoundsCheck(prepareBoundsCheck___d929));
module_specialRWALU instance_specialRWALU_4(.specialRWALU_cap(NOT_basicExec_dInst_BIT_32_7_8_AND_IF_basicExe_ETC___d740),
.specialRWALU_oldCap(basicExec_rVal2),
.specialRWALU_scrType(IF_basicExec_dInst_BITS_103_TO_101_50_EQ_0_51__ETC___d172),
@@ -900,16 +905,6 @@ module module_basicExec(basicExec_dInst,
((basicExec_dInst[139:137] == 3'd1) ?
!brAddrCalc___d258[162] :
!basicExec_rVal1[162]) ;
assign NOT_basicExec_dInst_BIT_75_86_87_OR_basicExec__ETC___d984 =
{ NOT_basicExec_dInst_BIT_75_86_87_OR_basicExec__ETC___d897 &&
(!basicExec_dInst[76] ||
_theResult___snd_capFat_address__h911[63:0] != 64'd0) &&
capChecks___d913[11],
capChecks___d913[10:5],
CASE_capChecks_13_BITS_4_TO_0_0_capChecks_13_B_ETC__q7,
NOT_basicExec_dInst_BIT_75_86_87_OR_basicExec__ETC___d897 &&
prepareBoundsCheck___d977[265],
prepareBoundsCheck___d977[264:0] } ;
assign _0_CONCAT_basicExec_pcc_BITS_159_TO_96_73_PLUS__ETC___d287 =
x__h2619[13:11] < repBound__h3837 ;
assign _theResult___snd_capFat_addrBits__h912 =
@@ -1929,26 +1924,6 @@ module module_basicExec(basicExec_dInst,
res_fst_capFat_flags__h527;
endcase
end
always@(basicExec_dInst or
res_fst_capFat_reserved__h528 or
basicExec_pcc or _theResult___snd_capFat_reserved__h915)
begin
case (basicExec_dInst[144:140])
5'd8, 5'd9, 5'd14:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 = 2'd0;
5'd11, 5'd13, 5'd18:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
res_fst_capFat_reserved__h528;
5'd12, 5'd15:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
basicExec_pcc[64:63];
5'd17:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
_theResult___snd_capFat_reserved__h915;
default: IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
2'd0;
endcase
end
always@(basicExec_dInst or
capModify___d210 or
basicExec_pcc or
@@ -1985,6 +1960,26 @@ module module_basicExec(basicExec_dInst,
IF_basicExec_dInst_BITS_144_TO_140_EQ_15_19_TH_ETC___d592;
endcase
end
always@(basicExec_dInst or
res_fst_capFat_reserved__h528 or
basicExec_pcc or _theResult___snd_capFat_reserved__h915)
begin
case (basicExec_dInst[144:140])
5'd8, 5'd9, 5'd14:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 = 2'd0;
5'd11, 5'd13, 5'd18:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
res_fst_capFat_reserved__h528;
5'd12, 5'd15:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
basicExec_pcc[64:63];
5'd17:
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
_theResult___snd_capFat_reserved__h915;
default: IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d567 =
2'd0;
endcase
end
always@(basicExec_dInst or
res_fst_capFat_perms_soft__h3311 or
basicExec_pcc or _theResult___snd_capFat_perms_soft__h3317)
@@ -2268,49 +2263,18 @@ module module_basicExec(basicExec_dInst,
3'd7;
endcase
end
always@(capChecks___d913)
begin
case (capChecks___d913[4:0])
5'd0,
5'd1,
5'd2,
5'd3,
5'd4,
5'd5,
5'd6,
5'd7,
5'd8,
5'd9,
5'd10,
5'd11,
5'd16,
5'd17,
5'd18,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24,
5'd25,
5'd26:
CASE_capChecks_13_BITS_4_TO_0_0_capChecks_13_B_ETC__q7 =
capChecks___d913[4:0];
default: CASE_capChecks_13_BITS_4_TO_0_0_capChecks_13_B_ETC__q7 = 5'd27;
endcase
end
always@(basicExec_dInst or
IF_basicExec_dInst_BITS_144_TO_140_EQ_15_19_TH_ETC___d549 or
res_fst_capFat_flags__h527 or basicExec_pcc)
begin
case (basicExec_dInst[144:140])
5'd11:
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q8 =
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q7 =
res_fst_capFat_flags__h527;
5'd12:
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q8 =
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q7 =
basicExec_pcc[65];
default: CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q8 =
default: CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q7 =
basicExec_dInst[144:140] != 5'd9 &&
basicExec_dInst[144:140] != 5'd14 &&
IF_basicExec_dInst_BITS_144_TO_140_EQ_15_19_TH_ETC___d549;
@@ -2333,7 +2297,7 @@ module module_basicExec(basicExec_dInst,
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d507 or
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d520 or
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d533 or
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q8 or
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q7 or
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d612 or
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_7_ETC___d626 or
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d640 or
@@ -2377,7 +2341,7 @@ module module_basicExec(basicExec_dInst,
basicExec_dInst[144:140] != 5'd8 &&
IF_basicExec_dInst_BITS_144_TO_140_EQ_11_THEN__ETC___d533,
basicExec_dInst[144:140] != 5'd8 &&
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q8,
CASE_basicExec_dInst_BITS_144_TO_140_11_res_fs_ETC__q7,
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_0_ETC___d612,
IF_basicExec_dInst_BITS_144_TO_140_EQ_8_THEN_7_ETC___d626,
basicExec_dInst[144:140] == 5'd8 ||