Provide opt-in wedge debugging info
When DEBUG_WEDGE is defined, expose the last committed and next in the reorder buffer PC and corresponding instruction via DMI registers, since even when the core is wedged and we can't read GPRs etc we can still interact with the debug module itself. Hopefully this proves useful for debugging wedges.
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@@ -201,6 +201,13 @@ interface Core;
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interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
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`endif
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`ifdef DEBUG_WEDGE
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(* always_enabled *)
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method Tuple2#(CapMem, Bit#(32)) debugLastInst;
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(* always_enabled *)
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method Tuple2#(CapMem, Bit#(32)) debugNextInst;
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`endif
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endinterface
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// fixpoint to instantiate modules
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@@ -1446,4 +1453,9 @@ module mkCore#(CoreId coreId)(Core);
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interface v_to_TV = map (toGet, v_f_to_TV);
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`endif
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`ifdef DEBUG_WEDGE
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method Tuple2#(CapMem, Bit#(32)) debugLastInst = commitStage.debugLastInst;
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method Tuple2#(CapMem, Bit#(32)) debugNextInst = rob.debugNextInst;
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`endif
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endmodule
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@@ -103,6 +103,11 @@ import ProcTypes :: *;
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import Trace_Data2 :: *;
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`endif
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`ifdef DEBUG_WEDGE
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import CHERICap :: *;
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import CHERICC_Fat :: *;
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`endif
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// ================================================================
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(* synthesize *)
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@@ -328,6 +333,11 @@ module mkProc (Proc_IFC);
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interface v_to_TV = core [0].v_to_TV;
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`endif
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`ifdef DEBUG_WEDGE
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method Tuple2#(CapMem, Bit#(32)) hart0_last_inst = core[0].debugLastInst;
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method Tuple2#(CapMem, Bit#(32)) hart0_next_inst = core[0].debugNextInst;
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`endif
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endmodule: mkProc
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// ================================================================
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@@ -46,6 +46,11 @@ import Trace_Data2 :: *;
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import Types :: *;
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`endif
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`ifdef DEBUG_WEDGE
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import CHERICap :: *;
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import CHERICC_Fat :: *;
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`endif
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// ================================================================
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// CPU interface
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@@ -128,6 +133,13 @@ interface Proc_IFC;
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interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
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`endif
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`ifdef DEBUG_WEDGE
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(* always_enabled *)
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method Tuple2#(CapMem, Bit#(32)) hart0_last_inst;
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(* always_enabled *)
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method Tuple2#(CapMem, Bit#(32)) hart0_next_inst;
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`endif
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endinterface
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// ================================================================
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