Provide opt-in wedge debugging info

When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.

src_Core/CPU/Proc.bsv

@@ -103,6 +103,11 @@ import ProcTypes   :: *;
 import Trace_Data2 :: *;
 `endif
 
+`ifdef DEBUG_WEDGE
+import CHERICap    :: *;
+import CHERICC_Fat :: *;
+`endif
+
 // ================================================================
 
 (* synthesize *)
@@ -328,6 +333,11 @@ module mkProc (Proc_IFC);
    interface v_to_TV = core [0].v_to_TV;
 `endif
 
+`ifdef DEBUG_WEDGE
+    method Tuple2#(CapMem, Bit#(32)) hart0_last_inst = core[0].debugLastInst;
+    method Tuple2#(CapMem, Bit#(32)) hart0_next_inst = core[0].debugNextInst;
+`endif
+
 endmodule: mkProc
 
 // ================================================================