Provide opt-in wedge debugging info

When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.

src_SSITH_P3/Makefile

@@ -40,6 +40,9 @@ BSC_COMPILATION_FLAGS += \
 	-D BRVF_TRACE \
 	-D XILINX_BSCAN  -D JTAG_TAP
 
+# Enable to expose last and next instruction info as DMI registers
+#BSC_COMPILATION_FLAGS += -D DEBUG_WEDGE
+
 # Synth only BSC_COMPILATION_FLAGS
 SYNTH_BSC_OPTIONS = -D XILINX_XCVU9P
 

src_SSITH_P3/src_BSV/JtagTap.bsv

@@ -13,7 +13,7 @@ import PowerOnReset ::*;
 import ClockHacks ::*;
 import Giraffe_IFC ::*;
 
-typedef 6 ABITS;
+typedef 7 ABITS;
 `ifdef XILINX_BSCAN
 `ifdef XILINX_XCVU095
 typedef 6 IR_LENGTH;