From 69c697daf7644ee9d120e4eb8fe1d1335be44a15 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 22 Oct 2020 15:21:47 +0100 Subject: [PATCH] Changes needed to build for FPGA. --- src_Core/CPU/Core.bsv | 2 +- .../RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 2 +- src_SSITH_P3/xilinx_ip/component.xml | 20 +++++++++++++++++++ 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 1c16a97..3e91399 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -1319,7 +1319,7 @@ module mkCore#(CoreId coreId)(Core); l2Tlb.updateVMInfo(vmI, vmD); let startpc = csrf.dpc_read; - fetchStage.redirect (cast(startpc)); + fetchStage.redirect (PredState{pc: cast(startpc)}); renameStage.debug_resume; commitStage.debug_resume; diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index f7b529e..e40eb1a 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -747,7 +747,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); ? 4 : 1)); csrf.dcsr_cause_write (dcsr_cause); - csrf.dpc_write (cast(trap.pc)); + csrf.dpc_write (cast(trap.ps.pc)); // Tell fetch stage to wait for redirect // Note: rule doCommitTrap_flush may have done this already; redundant call is ok. diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index 8a4b2e2..7f94e25 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -2696,6 +2696,26 @@ verilogSource IMPORTED_FILE + + hdl/module_capChecksExec.v + verilogSource + IMPORTED_FILE + + + hdl/module_capChecksMem.v + verilogSource + IMPORTED_FILE + + + hdl/mkAxiLowPower.v + verilogSource + IMPORTED_FILE + + + hdl/mkPLIC_16_CoreNumX2_7.v + verilogSource + IMPORTED_FILE + hdl/module_decode.v verilogSource