diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index 2432b63..88ad15e 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -64,7 +64,7 @@ typedef struct {
     InstTag tag;
     LdStQTag ldstq_tag;
     CapChecks cap_checks;
-    Bool cap_mode;
+    Bool ddc_offset;
 } MemDispatchToRegRead deriving(Bits, Eq, FShow);
 
 typedef struct {
@@ -402,7 +402,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                 tag: x.tag,
                 ldstq_tag: x.data.ldstq_tag,
                 cap_checks: x.data.cap_checks,
-                cap_mode: x.data.cap_mode
+                ddc_offset: x.data.ddc_offset
             },
             spec_bits: x.spec_bits
         });
@@ -431,7 +431,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
             rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
         end
-        if (!x.cap_mode) rVal1 = nullWithAddr(getAddr(rVal1) + getAddr(ddc));
+        if (x.ddc_offset) rVal1 = nullWithAddr(getAddr(rVal1) + getAddr(ddc));
 
         // get rVal2 (check bypass)
         CapPipe rVal2 = nullCap;
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
index 1535a39..58f39a4 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
@@ -677,7 +677,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
                             imm: validValue(dInst.imm),
                             ldstq_tag: lsqTag,
                             cap_checks: dInst.capChecks,
-                            cap_mode: dInst.execFunc.Mem.reg_bounds
+                            ddc_offset: !dInst.execFunc.Mem.reg_bounds
                         },
                         regs: phy_regs,
                         tag: inst_tag,
@@ -1017,7 +1017,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
                                             imm: validValue(dInst.imm),
                                             ldstq_tag: lsqTag,
                                             cap_checks: dInst.capChecks,
-                                            cap_mode: dInst.execFunc.Mem.reg_bounds
+                                            ddc_offset: !dInst.execFunc.Mem.reg_bounds
                                         },
                                         regs: phy_regs,
                                         tag: inst_tag,
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/ReservationStationMem.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/ReservationStationMem.bsv
index 5c51f54..cb0dc8d 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/ReservationStationMem.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/ReservationStationMem.bsv
@@ -32,7 +32,7 @@ typedef struct {
     ImmData imm;
     LdStQTag ldstq_tag;
     CapChecks cap_checks;
-    Bool cap_mode;
+    Bool ddc_offset;
 } MemRSData deriving(Bits, Eq, FShow);
 
 // MEM pipeline is aggressive, i.e. it recv bypass and early RS wakeup