From f46b9616748c989fff250b9040107cec43a0a744 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 21 Feb 2022 09:19:25 +0000 Subject: [PATCH 1/8] Bumped TagController --- libs/TagController | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/TagController b/libs/TagController index 99c43e8..df1b252 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 99c43e81384741ae11e098a63514a78bd43637e2 +Subproject commit df1b252e33f56fbba680e975d5911eb344541d58 From 90f236aab1f209c1804b8ae9e94bedaf4e954bc2 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 21 Feb 2022 14:39:44 +0000 Subject: [PATCH 2/8] Bumped BlueStuff, TagController and BSV-RVFI-DII --- libs/BlueStuff | 2 +- libs/TagController | 2 +- src_Verifier/BSV-RVFI-DII | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index a6e2273..8a36aa9 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit a6e2273920cadf21c54c16865d00dbd345b59b13 +Subproject commit 8a36aa9af4d35851053b6f474b959a340e9a72c7 diff --git a/libs/TagController b/libs/TagController index df1b252..2e2198b 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit df1b252e33f56fbba680e975d5911eb344541d58 +Subproject commit 2e2198b05f3c7cea61d690e3aa438211d0de9e8d diff --git a/src_Verifier/BSV-RVFI-DII b/src_Verifier/BSV-RVFI-DII index 8a15990..fbfe5a1 160000 --- a/src_Verifier/BSV-RVFI-DII +++ b/src_Verifier/BSV-RVFI-DII @@ -1 +1 @@ -Subproject commit 8a15990997e5391b447155757b5d60ecf13cc5bd +Subproject commit fbfe5a1c9d9d6cb5b6122d9ea1732b5a69ea7ed7 From 56c0ca328bab2e27d4c67a1113b11aa66ba14423 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 28 Feb 2022 13:03:00 +0000 Subject: [PATCH 3/8] Added missing update due to changing version of BlueStuff --- src_Testbench/SoC/SoC_Top.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index 4bb7e24..e854d53 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -209,7 +209,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) `ifdef INCLUDE_ACCEL0 // Fabric to accel0 - slave_vector[accel0_slave_num] = zeroSlaveUserFields (accel0.slave); + slave_vector[accel0_slave_num] = zero_AXI4_Slave_user(accel0.slave); route_vector[accel0_slave_num] = soc_map.m_accel0_addr_range; `endif From a6976c00712537b3adfc2dc05fe479bb0b2ea99f Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Wed, 9 Mar 2022 14:50:48 +0000 Subject: [PATCH 4/8] Fix RVFI-only build --- src_Core/CPU/Core.bsv | 13 ++++++++++++- src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 4 ++-- .../procs/RV64G_OOO/FpuMulDivExePipeline.bsv | 2 +- .../RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv | 4 ++-- src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv | 6 ++++-- 5 files changed, 21 insertions(+), 8 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 7ce2467..dd31fff 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -735,8 +735,19 @@ module mkCore#(CoreId coreId)(Core); endinterface); CommitStage commitStage <- mkCommitStage(commitInput); -`ifdef RVFI +`ifdef RVFI_DII mkConnection(commitStage.rvfi, rvfi_bridge.rvfi); +`else +`ifdef RVFI + // XXX Currently RVFI can only be connected to the outside world + // via the RVFI_DII bridge i.e. when DII is also being used. + rule drop; + let packets <- commitStage.rvfi.get(); + for (Integer i = 0; i < valueOf(SupSize); i = i+1) begin + if (isValid(packets[i])) $display("%t: RVFI ", $time, fshow(packets[i].Valid)); + end + endrule +`endif `endif // send rob enq time to reservation stations diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index 8e14907..192f844 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -199,7 +199,7 @@ typedef struct { Addr addr; Trap trap; Bit #(32) orig_inst; -`ifdef RVFI_DII +`ifdef RVFI ToReorderBuffer x; `endif } CommitTrap deriving(Bits, FShow); @@ -686,7 +686,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); pc: x.pc, addr: vaddr, orig_inst: x.orig_inst -`ifdef RVFI_DII +`ifdef RVFI , x: x `endif }); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv index 2434320..3059123 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv @@ -260,7 +260,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); data, `endif fflags -`ifdef RVFI_DII +`ifdef RVFI , ExtraTraceBundle{regWriteData: data, memByteEn: ?} `endif ); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index b4d79ec..ac1310c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -523,7 +523,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); }); endrule -`ifdef RVFI_DII +`ifdef RVFI Vector#(TExp#(SizeOf#(LdStQTag)), Reg#(Data)) memData <- replicateM(mkReg(?)); `endif @@ -538,7 +538,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); CapPipe data = x.rVal2; MemTaggedData toMemData = unpack(pack(toMem(data))); -`ifdef RVFI_DII +`ifdef RVFI memData[pack(x.ldstq_tag)] <= getAddr(data); $display("%t : memData[%x] <= %x", $time(), pack(x.ldstq_tag), getAddr(data)); `endif diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv index 9840277..e03a490 100644 --- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv @@ -46,7 +46,7 @@ import MemoryTypes::*; import CHERICap::*; import CHERICC_Fat::*; import ISA_Decls_CHERI::*; -`ifdef RVFI_DII +`ifdef RVFI import GetPut::*; import RVFI_DII_Types::*; `endif @@ -86,8 +86,10 @@ typedef struct { `endif } InstTag deriving(Bits, Eq, FShow); -`ifdef RVFI_DII +`ifdef RVFI typedef Vector#(SupSize, Maybe#(RVFI_DII_Execution #(64, 64))) Rvfi_Traces; +`endif +`ifdef RVFI_DII typedef Vector#(TMul#(SupSize, 2), RVFI_DII_Parcel_Resp) Dii_Parcel_Resps; typedef Vector#(TMul#(SupSize, 2), Bit#(16)) Dii_Parcels; From d005d4ea61f1b637d620d494795438621bb0c77d Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Wed, 9 Mar 2022 14:55:46 +0000 Subject: [PATCH 5/8] Bump BSV-RVFI-DII --- src_Verifier/BSV-RVFI-DII | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Verifier/BSV-RVFI-DII b/src_Verifier/BSV-RVFI-DII index fbfe5a1..b6aa39d 160000 --- a/src_Verifier/BSV-RVFI-DII +++ b/src_Verifier/BSV-RVFI-DII @@ -1 +1 @@ -Subproject commit fbfe5a1c9d9d6cb5b6122d9ea1732b5a69ea7ed7 +Subproject commit b6aa39d1c31ff56bc51eb740710cb603ae9be1a5 From 00c002147988c93bf27181c0da515bcf21088ebf Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Wed, 9 Mar 2022 14:58:11 +0000 Subject: [PATCH 6/8] Enable RVFI by default for bluesim builds --- builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile | 5 +++++ builds/Resources/Include_bluesim.mk | 2 ++ 2 files changed, 7 insertions(+) diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile index a29def0..5ef62de 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile @@ -3,6 +3,11 @@ REPO ?= ../.. ARCH ?= RV64ACDFIMSUxCHERI +# ================================================================ +# Path to RISCY-OOO sources not included in Common + +EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII + # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk index 75f09b5..2c63a15 100644 --- a/builds/Resources/Include_bluesim.mk +++ b/builds/Resources/Include_bluesim.mk @@ -15,6 +15,8 @@ build_dir: ifeq (,$(filter clean full_clean,$(MAKECMDGOALS))) include .depends.mk +BSC_COMPILATION_FLAGS += -D RVFI + .depends.mk: TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv | build_dir if ! bluetcl -exec makedepend -elab -sim $(TMP_DIRS) $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi endif From a6b39b58a1d3e702101cdf79df7f034a7528f498 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Fri, 11 Mar 2022 10:23:31 +0000 Subject: [PATCH 7/8] Clean up prints --- src_Core/CPU/Core.bsv | 2 +- src_Core/CPU/MMIO_AXI4_Adapter.bsv | 2 +- src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 5 +++-- src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 2 +- src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv | 2 -- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 2 -- src_Core/RISCY_OOO/procs/lib/DTlb.bsv | 9 +++++---- src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv | 3 +-- src_Testbench/Top/Mem_Model.bsv | 2 +- 9 files changed, 13 insertions(+), 16 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index dd31fff..ca468cc 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -744,7 +744,7 @@ module mkCore#(CoreId coreId)(Core); rule drop; let packets <- commitStage.rvfi.get(); for (Integer i = 0; i < valueOf(SupSize); i = i+1) begin - if (isValid(packets[i])) $display("%t: RVFI ", $time, fshow(packets[i].Valid)); + if (isValid(packets[i])) $display("%d: RVFI ", cur_cycle, fshow(packets[i].Valid)); end endrule `endif diff --git a/src_Core/CPU/MMIO_AXI4_Adapter.bsv b/src_Core/CPU/MMIO_AXI4_Adapter.bsv index a675509..633f61b 100644 --- a/src_Core/CPU/MMIO_AXI4_Adapter.bsv +++ b/src_Core/CPU/MMIO_AXI4_Adapter.bsv @@ -76,7 +76,7 @@ endinterface module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC); // Verbosity: 0: quiet; 1: transactions - Integer verbosity = 1; + Integer verbosity = 0; Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity)); // ================================================================ diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index efb03a5..a9083ad 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -483,8 +483,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); mispred: True, isCompressed: x.isCompressed }); - $display("alu mispredict pc¤: %x, nextPc: %x, %d", - x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle); + if (verbose) + $display("alu mispredict pc: %x, nextPc: %x, %d", + x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle); `ifdef PERF_COUNT // performance counter if(inIfc.doStats) begin diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index 192f844..36d75db 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -289,7 +289,7 @@ deriving (Eq, FShow, Bits); module mkCommitStage#(CommitInput inIfc)(CommitStage); Bool verbose = False; - Integer verbosity = 1; // Bluespec: for lightweight verbosity trace + Integer verbosity = 0; // Bluespec: for lightweight verbosity trace // Used to inform tandem-verifier about program order. // 0 is used to indicate we've just come out of reset diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index ac1310c..10426a3 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -540,7 +540,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); `ifdef RVFI memData[pack(x.ldstq_tag)] <= getAddr(data); - $display("%t : memData[%x] <= %x", $time(), pack(x.ldstq_tag), getAddr(data)); `endif // get shifted data and BE @@ -856,7 +855,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); `ifdef RVFI LdStQTag idx = tagged Ld tag; memData[pack(idx)] <= truncate(pack(res.data)); // TODO use fromMem? - $display("%t : memData[%x] <= %x", $time(), pack(idx), res.data); `endif end if(res.wrongPath) begin diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 0dd250c..42c133b 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -732,7 +732,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); doAssert((dInst.iType != Fence) == isValid(dInst.imm), "Mem (non-Fence) needs imm for virtual addr"); Bit#(16) dum = hash(getAddr(pc)); - $display("pc : %x , hash(pc) : %x", pc, dum); // put in ldstq if(isLdQ) begin lsq.enqLd(inst_tag, mem_inst, allow_cap, phy_regs.dst, spec_bits, hash(getAddr(pc))); @@ -1069,7 +1068,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); doAssert(!isValid(spec_tag), "should not have spec tag"); // put in ldstq Bit#(16) dum = hash(getAddr(pc)); - $display("pc : %x , hash(pc) : %x", pc, dum); if(isLdQ) begin lsq.enqLd(inst_tag, mem_inst, phy_regs.dst, spec_bits, hash(getAddr(pc))); end diff --git a/src_Core/RISCY_OOO/procs/lib/DTlb.bsv b/src_Core/RISCY_OOO/procs/lib/DTlb.bsv index aaa9df1..e24c47c 100644 --- a/src_Core/RISCY_OOO/procs/lib/DTlb.bsv +++ b/src_Core/RISCY_OOO/procs/lib/DTlb.bsv @@ -287,10 +287,11 @@ module mkDTlb#( end else if(pRs.entry matches tagged Valid .en) begin // check permission - $display("dPRs: vm_info: ", fshow(vm_info), - " en : ", fshow(en), - " r : ", fshow(r) - ); + if (verbose) + $display("dPRs: vm_info: ", fshow(vm_info), + " en : ", fshow(en), + " r : ", fshow(r) + ); let permCheck = hasVMPermission(vm_info, en.pteType, en.pteUpperType, diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index 194f570..70f5736 100644 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -674,7 +674,7 @@ module mkSupReorderBuffer#( Add#(1, a__, aluExeNum), Add#(1, b__, fpuMulDivExeNum) ); - Bool verbose = True; + Bool verbose = False; // doCommit rule: deq < wrongSpec (overwrite deq in doCommit) < doRenaming rule: enq Integer valid_deq_port = 0; @@ -756,7 +756,6 @@ module mkSupReorderBuffer#( // move deqP & reset valid deqP[i] <= getNextPtr(deqP[i]); valid[i][deqP[i]][valid_deq_port] <= False; - $display("deq[%d][%d]", i, deqP[i]); end end // update firstDeqWay: find the first deq port that is not enabled diff --git a/src_Testbench/Top/Mem_Model.bsv b/src_Testbench/Top/Mem_Model.bsv index f70c8d7..11dd23f 100644 --- a/src_Testbench/Top/Mem_Model.bsv +++ b/src_Testbench/Top/Mem_Model.bsv @@ -81,7 +81,7 @@ typedef Bit#(TSub#(TSub#(TLog#(TSub#(Zeroed_1_end, Zeroed_1_start)), LogZMWidth) (* synthesize *) module mkMem_Model (Mem_Model_IFC); - Integer verbosity = 1; // 0 = quiet; 1 = verbose + Integer verbosity = 0; // 0 = quiet; 1 = verbose Raw_Mem_Addr alloc_size = fromInteger(valueOf(TDiv#(TMul#(Bytes_Per_Mem,8), Bits_per_Raw_Mem_Word))); //(raw mem words) From d0c1d97a2afe1df8c850309a15893c1886d56081 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Tue, 15 Mar 2022 10:03:43 +0000 Subject: [PATCH 8/8] Print RVFI packets in RVFI_DII also --- src_Core/CPU/Core.bsv | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index ca468cc..b38439c 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -735,9 +735,6 @@ module mkCore#(CoreId coreId)(Core); endinterface); CommitStage commitStage <- mkCommitStage(commitInput); -`ifdef RVFI_DII - mkConnection(commitStage.rvfi, rvfi_bridge.rvfi); -`else `ifdef RVFI // XXX Currently RVFI can only be connected to the outside world // via the RVFI_DII bridge i.e. when DII is also being used. @@ -746,8 +743,10 @@ module mkCore#(CoreId coreId)(Core); for (Integer i = 0; i < valueOf(SupSize); i = i+1) begin if (isValid(packets[i])) $display("%d: RVFI ", cur_cycle, fshow(packets[i].Valid)); end - endrule +`ifdef RVFI_DII + rvfi_bridge.rvfi.put(packets); `endif + endrule `endif // send rob enq time to reservation stations