diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt index 9541ead..808a35e 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt @@ -20,15 +20,25 @@ Subtracting 0x80000000 base from addresses ./exe_HW_sim +v1 +tohost Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2112 to 33554430. 1: top.soc_top.rl_reset_start_initial ... +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle 11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 SoC address map: @@ -36,6 +46,7 @@ calling cycle Mem0 Controller: 0x80000000 .. 0xc0000000 UART0: 0xc0000000 .. 0xc0000080 11: top.soc_top.rl_reset_complete_initial +[stats] enabled 1 calling cycle ================================================================ Bluespec RISC-V standalone system simulation v1.2 @@ -43,1220 +54,2370 @@ Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. ================================================================ INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0 12: top.soc_top.method start (tohost 0, fromhost 0) +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle 100: top.soc_top.rl_step_0, n = 0, do_release 100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) 100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +[stats] enabled 1 calling cycle 101: top.soc_top.rl_ctrl_req 101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 101: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000 +[stats] enabled 1 calling cycle [RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000 instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 +[stats] enabled 1 calling cycle instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 +[stats] enabled 1 calling cycle instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[stats] enabled 1 calling cycle 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } Decoded delta = 0 DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False } +incrementing TLB counter +[stats] enabled 1 calling cycle Received delta = 0 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: , data: TaggedData { tag: , data: }, loadTags: False } +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000 [doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: }; TaggedData { tag: False, data: } +[stats] enabled 1 calling cycle instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +[stats] enabled 1 calling cycle [ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +[stats] enabled 1 calling cycle instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 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calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h02, rn2 'h07}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +[stats] enabled 1 calling cycle [RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 [RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapInspect GetBase, capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000 instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020002db iType:Auipcc [doCommitNormalInst [0]] 1155 instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155 [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +[stats] enabled 1 calling cycle [RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [RFile] wr_ 0: r 4a <= 0000000000000002000000001fffff44000000 [RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 11570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 +[stats] enabled 1 calling cycle [RFile] wr_ 1: r 4b <= 0000000020000400100000001ffff804021000 11580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x000043a1 iType:Alu [doCommitNormalInst [1]] 1158 +[stats] enabled 1 calling cycle [RFile] wr_ 0: r 4c <= 0000014020000400100000001ffff804021000 [RFile] wr_ 1: r 4f <= 0000000000000000400000001fffff44000000 11590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } Decoded delta = 10 DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False } +incrementing TLB counter 11590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } instret:11 PC:0x1ffff0000000000000000000080000012 instr:0x1071015b iType:Cap [doCommitNormalInst [0]] 1159 +[stats] enabled 1 calling cycle [RFile] wr_ 1: r 4d <= 0000014020000400000000001fffff44000000 Received delta = 10 @@ -1265,8 +2426,10 @@ Received delta = 10 11600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } Decoded delta = 0 DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } +incrementing TLB counter 11600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } instret:12 PC:0x1ffff0000000000000000000080000016 instr:0x00a1115b iType:Cap [doCommitNormalInst [0]] 1160 +[stats] enabled 1 calling cycle Received delta = 0 11610 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } @@ -1274,109 +2437,186 @@ Received delta = 0 11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } 11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace instret:13 PC:0x1ffff000000000000000000008000001a instr:0xfe210e5b iType:Cap [doCommitNormalInst [0]] 1161 +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle 11630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h000000008000100a, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle 12370 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h000000008000100a, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle 12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } 12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: @@ -1384,23 +2624,31 @@ calling cycle 12380 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } 12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle 12390 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } [RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h000000008000100a, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle instret:14 PC:0x1ffff000000000000000000008000001e instr:0x00006282 iType:Ld [doCommitNormalInst [0]] 1241 instret:15 PC:0x1ffff0000000000000000000080000020 instr:0x00004305 iType:Alu [doCommitNormalInst [1]] 1241 [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[stats] enabled 1 calling cycle [doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8022 }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle +[stats] enabled 1 calling cycle 1247: mmioPlatform.rl_tohost: 0x1 (= 1) PASS diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/text.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/text.txt deleted file mode 100644 index f6c3409..0000000 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/text.txt +++ /dev/null @@ -1,2653 +0,0 @@ -make -C ../../Tests/elf_to_hex -make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' -make[1]: 'elf_to_hex' is up to date. -make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' -../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex -c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file -Section .text : addr 80000000 to addr 80000030; size 0x 30 (= 48) bytes -Section .bss : addr 80010000 to addr 80010800; size 0x 800 (= 2048) bytes -Section .riscv.attributes: Ignored -Section .comment : Ignored -Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols -Writing symbols to: symbol_table.txt - No 'tohost' symbol found -Section .shstrtab : Ignored -Section .strtab : Ignored -Min addr: 80000000 (hex) -Max addr: 800107ff (hex) -Writing mem hex to file 'Mem.hex' -Subtracting 0x80000000 base from addresses -./exe_HW_sim +v1 +tohost -Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2112 to 33554430. -called -1: top.soc_top.rl_reset_start_initial ... -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 - SoC address map: - Boot ROM: 0x1000 .. 0x2000 - Mem0 Controller: 0x80000000 .. 0xc0000000 - UART0: 0xc0000000 .. 0xc0000080 -11: top.soc_top.rl_reset_complete_initial -calling cycle -called -================================================================ -Bluespec RISC-V standalone system simulation v1.2 -Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. -================================================================ -INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0 -12: top.soc_top.method start (tohost 0, fromhost 0) -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -100: top.soc_top.rl_step_0, n = 0, do_release -100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) -100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 -calling cycle -called -101: top.soc_top.rl_ctrl_req -101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 -101: top.soc_top do_release(restartRunning: True, to_host_addr: 0) -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -[RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000 -calling cycle -called -[RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000 -instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 -calling cycle -called -instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000 -calling cycle -called -instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -calling cycle -called - 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -Decoded delta = 0 -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False } -calling cycle -called -Received delta = 0 - 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 } -calling cycle -called -calling cycle -[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: , data: TaggedData { tag: , data: }, loadTags: False } -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000 -[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: }; TaggedData { tag: False, data: } -calling cycle -called -instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 -calling cycle -called -calling cycle -called -calling cycle -called -[ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -calling cycle -called -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -called -instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h02, rn2 'h07}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -called -[RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 -[RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapInspect GetBase, capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -called -[RFile] wr_ 1: r 47 <= 0000000000020000400000001fffff44000000 -instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x020002db iType:Auipcc [doCommitNormalInst [0]] 1155 -instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1155 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -called -[RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 -instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called -[RFile] wr_ 0: r 4a <= 0000000000000002000000001fffff44000000 -[RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 - 11570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 -calling cycle -called -[RFile] wr_ 1: r 4b <= 0000000020000400100000001ffff804021000 - 11580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } - 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 -instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x000043a1 iType:Alu [doCommitNormalInst [1]] 1158 -calling cycle -called -[RFile] wr_ 0: r 4c <= 0000014020000400100000001ffff804021000 -[RFile] wr_ 1: r 4f <= 0000000000000000400000001fffff44000000 - 11590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -Decoded delta = 10 -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False } - 11590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -instret:11 PC:0x1ffff0000000000000000000080000012 instr:0x1071015b iType:Cap [doCommitNormalInst [0]] 1159 -calling cycle -called -[RFile] wr_ 1: r 4d <= 0000014020000400000000001fffff44000000 -Received delta = 10 - 11600 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h000000a, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 } - 11600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h000000008000100a, shiftedBE: tagged DataMemAccess , pcHash: 'h801e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 11600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -Decoded delta = 0 -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } - 11600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } -instret:12 PC:0x1ffff0000000000000000000080000016 instr:0x00a1115b iType:Cap [doCommitNormalInst [0]] 1160 -calling cycle -called -Received delta = 0 - 11610 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } - 11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } - 11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -instret:13 PC:0x1ffff000000000000000000008000001a instr:0xfe210e5b iType:Cap [doCommitNormalInst [0]] 1161 -calling cycle -called -calling cycle - 11630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h000000008000100a, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called -calling cycle -called -calling cycle -called -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 12370 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h000000008000100a, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - 12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } - 12380 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - 12390 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h000000008000100a, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called -instret:14 PC:0x1ffff000000000000000000008000001e instr:0x00006282 iType:Ld [doCommitNormalInst [0]] 1241 -instret:15 PC:0x1ffff0000000000000000000080000020 instr:0x00004305 iType:Alu [doCommitNormalInst [1]] 1241 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -called -[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8022 }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } -calling cycle -called -calling cycle -called -calling cycle -called -1247: mmioPlatform.rl_tohost: 0x1 (= 1) -PASS diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 961d6f8..de2968e 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -963,6 +963,7 @@ module mkCore#(CoreId coreId)(Core); // broadcast whether we should collect data rule broadcastDoStats; let stats = csrf.doPerfStats; + $display("[stats] enabled %0d", csrf.doPerfStats); doStats <= stats; iMem.perf.setStatus(stats); dMem.perf.setStatus(stats);