From 6e00bd627b69ff2deeab5e628b58b96b19595e66 Mon Sep 17 00:00:00 2001 From: jon Date: Mon, 11 May 2020 12:21:57 +0100 Subject: [PATCH] Implement x0 default value in the memory pipe. --- src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index 75ced9f..5b1f78a 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -423,14 +423,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); let regsReady = inIfc.sbCons_lazyLookup(x.regs); // get rVal1 (check bypass) - CapPipe rVal1 = ?; - if(x.regs.src1 matches tagged Valid .src1) begin + CapPipe rVal1 = nullCap; + if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire); end // get rVal2 (check bypass) - CapPipe rVal2 = ?; - if(x.regs.src2 matches tagged Valid .src2) begin + CapPipe rVal2 = nullCap; + if(x.regs.src2 matches tagged Valid .src2 &&& src2 != 0) begin rVal2 <- readRFBypass(src2, regsReady.src2, inIfc.rf_rd2(src2), bypassWire); end