diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
index 9653706..7026aeb 100644
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
@@ -22,7 +22,7 @@ BSC_COMPILATION_FLAGS += \
 	-D FABRIC64    \
 	-D CheriBusBytes=8 \
 	-D CheriMasterIDWidth=1 \
-	-D CheriTransactionIDWidth=5 \
+	-D CheriTransactionIDWidth=6 \
 	-D CAP128 -D BLUESIM \
 	-D MEM64 \
 	-D RISCV \
diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk
index 19a5fec..78e580f 100644
--- a/builds/Resources/Include_Common.mk
+++ b/builds/Resources/Include_Common.mk
@@ -90,7 +90,7 @@ BSC_COMPILATION_FLAGS += \
 	-D FABRIC64    \
 	-D CheriBusBytes=8 \
 	-D CheriMasterIDWidth=1 \
-	-D CheriTransactionIDWidth=5 \
+	-D CheriTransactionIDWidth=6 \
 	-D CAP128 -D BLUESIM \
 	-D MEM64 \
 	-D RISCV \
diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv
index 414c3a7..818b562 100644
--- a/src_Testbench/SoC/SoC_Top.bsv
+++ b/src_Testbench/SoC/SoC_Top.bsv
@@ -93,7 +93,7 @@ import Debug_Module     :: *;
 interface SoC_Top_IFC;
 
 `ifdef INCLUDE_GDB_CONTROL
-  interface AXI4Lite_Slave #(7, 32, 0, 0, 0, 0, 0) debug_subordinate;
+  interface AXI4Lite_Slave #(21, 32, 0, 0, 0, 0, 0) debug_subordinate;
 `endif
 
 `ifdef INCLUDE_TANDEM_VERIF