From 6ea5d34d062adcf59255495207daed8c027dba8d Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Tue, 25 Jan 2022 17:05:34 +0000 Subject: [PATCH] Bump Bluestuff. --- libs/BlueStuff | 2 +- src_Core/Core/CoreW.bsv | 7 ++++--- src_Testbench/SoC/SoC_Top.bsv | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index df2529d..a6e2273 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit df2529dd4298fe77cfba638001f4a960f82fbe02 +Subproject commit a6e2273920cadf21c54c16865d00dbd345b59b13 diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index ba38045..9d058d6 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -59,6 +59,7 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Routable :: *; import AXI4 :: *; +import AXI4_Utils :: *; import TagControllerAXI :: *; import CacheCore :: *; @@ -171,7 +172,7 @@ module mkCoreW #(Reset dm_power_on_reset) Proc_IFC proc <- mkProc (reset_by all_harts_reset); // handle uncached interface - let proc_uncached = extendIDFields (zeroMasterUserFields (proc.master1), 0); + let proc_uncached = prepend_AXI4_Master_id (0, zero_AXI4_Master_user (proc.master1)); // Bridge for uncached expernal bus transactions. let uncached_mem_shim <- mkAXI4ShimFF(reset_by all_harts_reset); @@ -388,7 +389,7 @@ module mkCoreW #(Reset dm_power_on_reset) //let slave_vector = newVector; slave_vector[default_slave_num] = uncached_mem_shim.slave; slave_vector[llc_slave_num] = proc.debug_module_mem_server; - slave_vector[plic_slave_num] = zeroSlaveUserFields (plic.axi4_slave); + slave_vector[plic_slave_num] = zero_AXI4_Slave_user (plic.axi4_slave); function Vector#(Num_Slaves_2x3, Bool) route_2x3 (Bit#(Wd_Addr) addr); Vector#(Num_Slaves_2x3, Bool) res = replicate(False); @@ -459,7 +460,7 @@ module mkCoreW #(Reset dm_power_on_reset) interface cpu_imem_master = tagController.master; // Uncached master to Fabric master interface - interface cpu_dmem_master = extendIDFields(zeroMasterUserFields(uncached_mem_shim.master), 0); + interface cpu_dmem_master = prepend_AXI4_Master_id(0, zero_AXI4_Master_user(uncached_mem_shim.master)); // ---------------------------------------------------------------- // External interrupt sources diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index 3fbd43f..4bb7e24 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -204,7 +204,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) route_vector[mem0_controller_slave_num] = soc_map.m_mem0_controller_addr_range; // Fabric to UART0 - slave_vector[uart0_slave_num] = zeroSlaveUserFields(uart0.slave); + slave_vector[uart0_slave_num] = zero_AXI4_Slave_user(uart0.slave); route_vector[uart0_slave_num] = soc_map.m_uart0_addr_range; `ifdef INCLUDE_ACCEL0