diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 39be25c..2196fcb 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -1099,7 +1099,7 @@ module mkCore#(CoreId coreId)(Core);
      Reg#(EventsCache) events_tgc_reg <- mkRegU;
      rule report_events;
          EventsCore events = unpack(pack(commitStage.events));
-         events.evt_REDIRECT = fetchStage.redirect_evt;
+         events.evt_REDIRECT = zeroExtend(pack(fetchStage.redirect_evt));
          hpm_core_events[1] <= events;
      endrule
 
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index 895ffd9..2be2e48 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -419,7 +419,7 @@ module mkFetchStage(FetchStage);
     endrule
 `endif
 `ifdef PERFORMANCE_MONITORING
-    Reg#(Bool) redirect_evt <- mkDReg(False);
+    Reg#(Bool) redirect_evt_reg <- mkDReg(False);
 `endif
 
     rule updatePcInBtb;
@@ -905,7 +905,7 @@ module mkFetchStage(FetchStage);
         // we conservatively set wait for flush TODO make this an input parameter
         waitForFlush[2] <= True;
 `ifdef PERFORMANCE_MONITORING
-        redirect_evt <= True;
+        redirect_evt_reg <= True;
 `endif
     endmethod
 
@@ -1006,6 +1006,6 @@ module mkFetchStage(FetchStage);
     endinterface
 
 `ifdef PERFORMANCE_MONITORING
-    method Bool redirect_evt = redirect_evt._read;
+    method Bool redirect_evt = redirect_evt_reg._read;
 `endif
 endmodule