diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv
index fb94ad4..5248a37 100644
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -177,8 +177,10 @@ module mkP3_Core (P3_Core_IFC);
            , AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) )
      wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth);
    match {.wideS, .narrowM} = wideS_narrowM;
-   let master0_inOrder <- mkAXI4SingleIDMaster(corew.manager_0);
-   mkConnection(master0_inOrder, wideS);
+   AXI4_Shim#(TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
+       manager_0_deburster <- mkBurstToNoBurst;
+   mkConnection(corew.manager_0, manager_0_deburster.slave);
+   mkConnection(manager_0_deburster.master, wideS);
 
    // ================================================================
    // Delay DRAM to compensate for relatively lower FPGA clock
diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv
index d805646..6df676b 100644
--- a/src_Testbench/SoC/SoC_Top.bsv
+++ b/src_Testbench/SoC/SoC_Top.bsv
@@ -169,8 +169,10 @@ module mkSoC_Top #(Reset dm_power_on_reset)
            , AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) )
      wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth);
    match {.wideS, .narrowM} = wideS_narrowM;
-   let master0_inOrder <- mkAXI4SingleIDMaster(corew.manager_0);
-   mkConnection(master0_inOrder, wideS);
+   AXI4_Shim#(TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
+       manager_0_deburster <- mkBurstToNoBurst;
+   mkConnection(corew.manager_0, manager_0_deburster.slave);
+   mkConnection(manager_0_deburster.master, wideS);
 
    // SoC IPs
    UART_IFC   uart0  <- mkUART;