From 7d7d38ad49f654086045b185fcc3e43cfaa9bda8 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Fri, 24 Mar 2023 15:11:08 +0000 Subject: [PATCH 1/3] Repurpose L1D store miss count to track number of cycles cache is full --- src_Core/RISCY_OOO/coherence/src/L1Bank.bsv | 25 ++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv index 9b3e245..269ca73 100644 --- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv @@ -191,6 +191,12 @@ module mkL1Bank#( let prefetcher <- mkL1DPrefetcher; let llcPrefetcher <- mkLLDPrefetcherInL1D; + Count#(Bit#(8)) addedCRqs <- mkCount(0); + Count#(Bit#(8)) removedCRqs <- mkCount(0); + + Count#(Bit#(64)) currentFullCacheCycles <- mkCount(0); + Reg#(Bit#(64)) lastReportedFullCacheCycles <- mkReg(0); + // security flush `ifdef SECURITY_CACHES Reg#(Bool) flushDone <- mkReg(True); @@ -233,6 +239,9 @@ action `endif `ifdef PERFORMANCE_MONITORING EventsL1D events = unpack (0); + events.evt_ST_MISS = saturating_truncate(currentFullCacheCycles - lastReportedFullCacheCycles); + lastReportedFullCacheCycles <= currentFullCacheCycles; + $display("Reporting full cache cycles: %d", events.evt_ST_MISS); case(op) Ld: events.evt_LD = 1; St: events.evt_ST = 1; @@ -274,7 +283,7 @@ action end St: begin events.evt_ST_MISS_LAT = saturating_truncate(lat); - events.evt_ST_MISS = 1; + //events.evt_ST_MISS = 1; end Lr, Sc, Amo: begin events.evt_AMO_MISS_LAT = saturating_truncate(lat); @@ -305,6 +314,7 @@ endfunction mshrIdx: n })); cRqIsPrefetch[n] <= False; + addedCRqs.incr(1); if (verbose) $display("%t L1 %m cRqTransfer_retry: ", $time, fshow(n), " ; ", @@ -318,6 +328,7 @@ endfunction rule cRqTransfer_new(!cRqRetryIndexQ.notEmpty && flushDone); procRqT r <- toGet(rqFromCQ).get; cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r); + addedCRqs.incr(1); // send to pipeline pipeline.send(CRq (L1PipeRqIn { addr: r.addr, @@ -363,6 +374,14 @@ endfunction endrule + rule print_cRqIndexQ_len; + //$display("L1D cRqIndexQ length= %d", addedCRqs-removedCRqs); + endrule + + rule incrFullCacheCycles (addedCRqs - removedCRqs == 8); + currentFullCacheCycles.incr(1); + endrule + (* descending_urgency = "pRsTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *) (* descending_urgency = "pRqTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *) rule createPrefetchRq(flushDone); @@ -379,6 +398,7 @@ endfunction pcHash: ? }; cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r); + addedCRqs.incr(1); // send to pipeline pipeline.send(CRq (L1PipeRqIn { addr: r.addr, @@ -649,6 +669,7 @@ endfunction ); // release MSHR entry cRqMshr.pipelineResp.releaseEntry(n); + removedCRqs.incr(1); end else begin processAmo <= Valid (AmoHitInfo { @@ -711,6 +732,7 @@ endfunction ); // release MSHR entry cRqMshr.pipelineResp.releaseEntry(n); + removedCRqs.incr(1); // reset state processAmo <= Invalid; endrule @@ -752,6 +774,7 @@ endfunction end // release MSHR entry cRqMshr.pipelineResp.releaseEntry(n); + removedCRqs.incr(1); if (verbose) $display("%t L1 %m pipelineResp: Sc early fail func: ", $time, fshow(resetOwner), " ; ", From 96bed3532e492179c318c033a3003e1486ae2c9f Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Fri, 24 Mar 2023 15:11:39 +0000 Subject: [PATCH 2/3] Config for L1D StrideV2-2 prefetcher --- builds/Resources/Include_RISCY_Config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk index 9646934..fa3edb1 100644 --- a/builds/Resources/Include_RISCY_Config.mk +++ b/builds/Resources/Include_RISCY_Config.mk @@ -48,7 +48,7 @@ RENAME_DEBUG ?= false INSTR_PREFETCHER_LOCATION ?= NONE INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW DATA_PREFETCHER_LOCATION ?= L1 -DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT +DATA_PREFETCHER_TYPE ?= STRIDE # clk frequency depends on core size ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM)) From 06651f1a315342ee1064ae7d9ff07dec5d28df7c Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Fri, 24 Mar 2023 15:15:03 +0000 Subject: [PATCH 3/3] Actually repurpose L1D store count, not store miss count --- src_Core/RISCY_OOO/coherence/src/L1Bank.bsv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv index 269ca73..28ccb6c 100644 --- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv @@ -239,12 +239,12 @@ action `endif `ifdef PERFORMANCE_MONITORING EventsL1D events = unpack (0); - events.evt_ST_MISS = saturating_truncate(currentFullCacheCycles - lastReportedFullCacheCycles); + events.evt_ST = saturating_truncate(currentFullCacheCycles - lastReportedFullCacheCycles); lastReportedFullCacheCycles <= currentFullCacheCycles; - $display("Reporting full cache cycles: %d", events.evt_ST_MISS); + $display("Reporting full cache cycles: %d", events.evt_ST); case(op) Ld: events.evt_LD = 1; - St: events.evt_ST = 1; + //St: events.evt_ST = 1; Lr, Sc, Amo: events.evt_AMO = 1; endcase perf_events[0] <= events; @@ -283,7 +283,7 @@ action end St: begin events.evt_ST_MISS_LAT = saturating_truncate(lat); - //events.evt_ST_MISS = 1; + events.evt_ST_MISS = 1; end Lr, Sc, Amo: begin events.evt_AMO_MISS_LAT = saturating_truncate(lat);