diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 74b8743..112cf18 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 74b87433524be9c28d545d370c3812100bc56232 +Subproject commit 112cf18a33edfb7402782bcf297aa3d179f7e81a diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index e68bbf5..eb7c781 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -60,7 +60,8 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Routable :: *; import AXI4 :: *; -import AXI4_Utils :: *; +import AXI4Lite :: *; +import SourceSink :: *; import TagControllerAXI :: *; import CacheCore :: *; @@ -118,15 +119,18 @@ typedef WindCoreMid #( // AXI manager 0 port parameters // AXI subordinate 0 port parameters , 0, 0, 0, 0, 0, 0, 0, 0 // Number of interrupt lines - , N_External_Interrupt_Sources) WindCoreMidIfc; + , t_n_irq) CoreW_IFC #(numeric type t_n_irq); //(* synthesize *) -module mkCoreW (WindCoreMidIfc); - Reset dfltRst <- exposeCurrentReset; - Reset otherRst = ?; - match {.fromDbgReset, .ifc} <- mkCoreResetHelper ( dfltRst - , reset_by otherRst ); - otherRst <- mkResetEither (dfltRst, fromDbgReset); +module mkCoreW (CoreW_IFC #(t_n_irq)); + Clock clk <- exposeCurrentClock; + Reset rst <- exposeCurrentReset; + let newRst <- mkReset (0, True, clk, reset_by rst); + match {.otherRst, .ifc} <- mkCoreResetHelper ( rst + , reset_by newRst.new_rst); + rule rl_forward_debug_reset (otherRst); + newRst.assertReset; + endrule return ifc; endmodule @@ -134,7 +138,7 @@ endmodule // hacks to the nicer outer interface, and not have to use a large amount of // reset_by to decouple the debug module from the rest... module mkCoreResetHelper #(Reset toDbgReset) - (Tuple2#(Reset, WindCoreMidIfc)); + (Tuple2#(PulseWire, CoreW_IFC #(t_n_irq))); // ================================================================ // Notes on 'reset' @@ -447,36 +451,36 @@ module mkCoreResetHelper #(Reset toDbgReset) // ================================================================ // Connect external debug module interface - let f_dbg_reqs <- mkFIFO1; - let f_dbg_rsps <- mkFIFO1; + let dbgShim <- mkAXI4LiteShim (reset_by toDbgReset); - rule rl_debug_module_req; - case (f_dbg_reqs.first) matches - tagged ReadReq {.rd_addr}: debug_module.dmi.read_addr (rd_addr); - tagged WriteReq {.wr_addr, .wr_data}: - debug_module.dmi.write (wr_addr, wr_data); - endcase - f_dbg_reqs.deq; + rule rl_debug_module_read_req; + let arFlit <- get (dbgShim.master.ar); + debug_module.dmi.read_addr (arFlit.araddr); endrule - - rule rl_debug_module_rsp; + rule rl_debug_module_read_rsp; let x <- debug_module.dmi.read_data; - f_dbg_rsps.enq (ReadRsp(x)); + dbgShim.master.r.put(AXI4Lite_RFlit { rdata: x, rresp: OKAY, ruser: ?}); + endrule + rule rl_debug_module_write_req; + let awFlit <- get (dbgShim.master.aw); + let wFlit <- get (dbgShim.master.w); + dbgShim.master.b.put(defaultValue); + debug_module.dmi.write (awFlit.awaddr, wFlit.wdata); endrule - let fromDbgReset <- mkReset (0, False, clk); + let fromDbgReset <- mkPulseWire (reset_by toDbgReset); rule rl_debug_module_send_reset; let _ <- debug_module.ndm_reset_client.request.get; - fromDbgReset.assertReset; + fromDbgReset.send; endrule // ================================================================ // Connect external interrupts to the PLIC and Proc - Vector #(N_External_Interrupt_Sources, Reg #(Bool)) irq_reg + Vector #(t_n_irq, Reg #(Bool)) irq_reg <- replicateM (mkReg (False)); - Vector #(N_External_Interrupt_Sources, Put #(Bool)) irq_ifc; - for (Integer i = 0; i < valueof (N_External_Interrupt_Sources); i = i + 1) begin + Vector #(t_n_irq, Put #(Bool)) irq_ifc; + for (Integer i = 0; i < valueof (t_n_irq); i = i + 1) begin irq_ifc [i] = interface Put; method put = writeReg (irq_reg[i]); endinterface; @@ -523,10 +527,10 @@ module mkCoreResetHelper #(Reset toDbgReset) // ================================================================ // INTERFACE - let ifc = interface WindCoreMidIfc; + let ifc = interface CoreW_IFC; // debug related signals // --------------------- - interface debugModuleServer = toGPServer (f_dbg_reqs, f_dbg_rsps); + interface debug_subordinate = dbgShim.slave; // interrupt related signals // ------------------------- @@ -566,7 +570,7 @@ module mkCoreResetHelper #(Reset toDbgReset) `endif */ - return tuple2 (fromDbgReset.new_rst, ifc); + return tuple2 (fromDbgReset, ifc); endmodule: mkCoreResetHelper // ================================================================ diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv deleted file mode 100644 index ff6a4c3..0000000 --- a/src_Core/Core/CoreW_IFC.bsv +++ /dev/null @@ -1,204 +0,0 @@ -// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved. -// -//- -// RVFI_DII + CHERI modifications: -// Copyright (c) 2020 Alexandre Joannou -// Copyright (c) 2020 Peter Rugg -// Copyright (c) 2020 Jonathan Woodruff -// All rights reserved. -// -// This software was developed by SRI International and the University of -// Cambridge Computer Laboratory (Department of Computer Science and -// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the -// DARPA SSITH research programme. -// -// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). -//- - -package CoreW_IFC; - -// ================================================================ -// This package defines the interface of a CoreW module which -// contains: -// - mkProc (the RISC-V CPU; this a variant of MIT's RISCY-OOO mkProc) -// Note: MIT's RISCY-OOO internally has a 'mkCore' and hence this -// interface and its module is called 'CoreW', to disambiguate. -// - mkFabric_2x3 -// - mkNear_Mem_IO_AXI4 -// - mkPLIC_16_CoreNumX2_7 -// - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF) -// - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL) - -// ================================================================ -// BSV library imports - -import Vector :: *; -import GetPut :: *; -import ClientServer :: *; - -// ---------------- -// BSV additional libs -import AXI4 :: *; - -// ================================================================ -// Project imports - -// Main fabric -import Fabric_Defs :: *; - -// External interrupt request interface -import PLIC :: *; - -`ifdef INCLUDE_GDB_CONTROL -import Debug_Module :: *; -`endif - -`ifdef RVFI_DII -import ProcTypes :: *; -`endif - -`ifdef INCLUDE_TANDEM_VERIF -import ProcTypes :: *; -import Trace_Data2 :: *; -import TV_Info :: *; -`endif - -// ================================================================ -// The CoreW interface - -interface CoreW_IFC #(numeric type t_n_interrupt_sources); - - // ---------------------------------------------------------------- - // Debugging: set core's verbosity - - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - - // ---------------------------------------------------------------- - // Start - - method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); - - // ---------------------------------------------------------------- - // AXI4 Fabric interfaces - - // CPU IMem to Fabric master interface - interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_imem_master; - - // CPU DMem to Fabric master interface - interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_dmem_master; - - // ---------------------------------------------------------------- - // External interrupt sources - - interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources; - - // ---------------------------------------------------------------- - // Non-maskable interrupt request - - (* always_ready, always_enabled *) - method Action nmi_req (Bool set_not_clear); - -`ifdef RVFI_DII - interface Toooba_RVFI_DII_Server rvfi_dii_server; -`endif - -`ifdef INCLUDE_GDB_CONTROL - // ---------------------------------------------------------------- - // Optional Debug Module interfaces - - // ---------------- - // DMI (Debug Module Interface) facing remote debugger - - interface DMI dmi; - - // ---------------- - // Facing Platform - // Non-Debug-Module Reset (reset all except DM) - - interface Client #(Bool, Bool) ndm_reset_client; -`endif - -`ifdef INCLUDE_TANDEM_VERIF - // ---------------------------------------------------------------- - // Optional Tandem Verifier interface output tuples (n,vb), - // where 'vb' is a vector of bytes - // with relevant bytes in locations [0]..[n-1] - - interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get; -`endif - -endinterface - -// ================================================================ -// The Synthesizable CoreW interface (same with Synth AXI) - -interface CoreW_IFC_Synth #(numeric type t_n_interrupt_sources); - - // ---------------------------------------------------------------- - // Debugging: set core's verbosity - - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - - // ---------------------------------------------------------------- - // Start - - method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); - - // ---------------------------------------------------------------- - // AXI4 Fabric interfaces - - // CPU IMem to Fabric master interface - interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_imem_master; - - // CPU DMem to Fabric master interface - interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_dmem_master; - - // ---------------------------------------------------------------- - // External interrupt sources - - interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources; - - // ---------------------------------------------------------------- - // Non-maskable interrupt request - - (* always_ready, always_enabled *) - method Action nmi_req (Bool set_not_clear); - -`ifdef RVFI_DII - interface Toooba_RVFI_DII_Server rvfi_dii_server; -`endif - -`ifdef INCLUDE_GDB_CONTROL - // ---------------------------------------------------------------- - // Optional Debug Module interfaces - - // ---------------- - // DMI (Debug Module Interface) facing remote debugger - - interface DMI dmi; - - // ---------------- - // Facing Platform - // Non-Debug-Module Reset (reset all except DM) - - interface Client #(Bool, Bool) ndm_reset_client; -`endif - -`ifdef INCLUDE_TANDEM_VERIF - // ---------------------------------------------------------------- - // Optional Tandem Verifier interface output tuples (n,vb), - // where 'vb' is a vector of bytes - // with relevant bytes in locations [0]..[n-1] - - interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get; -`endif - -endinterface - -// ================================================================ - -endpackage diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index e854d53..daf6de8 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -47,6 +47,7 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Routable :: *; import AXI4 :: *; +import AXI4Lite :: *; // ================================================================ // Project imports @@ -56,7 +57,7 @@ import SoC_Map :: *; // SoC components (CPU, mem, and IPs) -import CoreW_IFC :: *; +import WindCoreInterface :: *; import CoreW :: *; import PLIC :: *; // For interface to PLIC interrupt sources, in CoreW_IFC @@ -90,15 +91,9 @@ import Debug_Module :: *; // The outermost interface of the SoC interface SoC_Top_IFC; - // Set core's verbosity - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); `ifdef INCLUDE_GDB_CONTROL - // DMI (Debug Module Interface) facing remote debugger - interface DMI dmi; - - // Non-Debug-Module Reset (reset all except DM) - interface Client #(Bool, Bool) ndm_reset_client; + interface AXI4Lite_Slave #(7, 32, 0, 0, 0, 0, 0) debug_subordinate; `endif `ifdef INCLUDE_TANDEM_VERIF @@ -148,7 +143,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) // Core: CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional) // The Debug Module has its own RST_N reset signal (which comes // from outside this module as a paramter) - CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW (dm_power_on_reset); + CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW; // SoC Boot ROM Boot_ROM_IFC boot_rom <- mkBoot_ROM; @@ -179,10 +174,10 @@ module mkSoC_Top #(Reset dm_power_on_reset) master_vector = newVector; // CPU IMem master to fabric - master_vector[imem_master_num] = corew.cpu_imem_master; + master_vector[imem_master_num] = corew.manager_0; // CPU DMem master to fabric - master_vector[dmem_master_num] = corew.cpu_dmem_master; + master_vector[dmem_master_num] = corew.manager_1; // ---------------- // SoC fabric slave connections @@ -232,21 +227,21 @@ module mkSoC_Top #(Reset dm_power_on_reset) Bool intr = uart0.intr; // UART - corew.core_external_interrupt_sources [irq_num_uart0].m_interrupt_req (intr); + corew.irq [irq_num_uart0].put (intr); Integer last_irq_num = irq_num_uart0; `ifdef INCLUDE_ACCEL0 Bool intr_accel0 = accel0.interrupt_req; - corew.core_external_interrupt_sources [irq_num_accel0].m_interrupt_req (intr_accel0); + corew.irq [irq_num_accel0].put (intr_accel0); last_irq_num = irq_num_accel0; `endif // Tie off remaining interrupt request lines (1..N) for (Integer j = last_irq_num + 1; j < valueOf (N_External_Interrupt_Sources); j = j + 1) - corew.core_external_interrupt_sources [j].m_interrupt_req (False); + corew.irq [j].put (False); // Non-maskable interrupt request. [Tie-off; TODO: connect to genuine sources] - corew.nmi_req (False); + corew.nmirq.put (False); endrule // ================================================================ @@ -314,17 +309,9 @@ module mkSoC_Top #(Reset dm_power_on_reset) // ================================================================ // INTERFACE - method Action set_verbosity (Bit #(4) new_verbosity, Bit #(64) logdelay); - corew.set_verbosity (new_verbosity, logdelay); - endmethod - // To external controller (E.g., GDB) `ifdef INCLUDE_GDB_CONTROL - // DMI (Debug Module Interface) facing remote debugger - interface DMI dmi = corew.dmi; - - // Non-Debug-Module Reset (reset all except DM) - interface Client ndm_reset_client = corew.ndm_reset_client; + interface debug_subordinate = corew.debug_subordinate; `endif `ifdef INCLUDE_TANDEM_VERIF @@ -352,7 +339,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) Bool watch_tohost = (tohost_addr != 0); mem0_controller.set_watch_tohost (watch_tohost, tohost_addr); Bool is_running = True; - corew.start (is_running, tohost_addr, fromhost_addr); + corew.controlStatusServer.request.put (ReleaseReq); $display ("%0d: %m.method start (tohost %0h, fromhost %0h)", cur_cycle, tohost_addr, fromhost_addr); endmethod diff --git a/src_Testbench/Top/Top_HW_Side.bsv b/src_Testbench/Top/Top_HW_Side.bsv index cc95e98..c93b966 100644 --- a/src_Testbench/Top/Top_HW_Side.bsv +++ b/src_Testbench/Top/Top_HW_Side.bsv @@ -51,6 +51,9 @@ import GetPut_Aux :: *; // ================================================================ // Project imports +import WindCoreInterface :: *; +import AXI4Lite :: *; +import SourceSink :: *; import ISA_Decls :: *; import TV_Info :: *; import SoC_Top :: *; @@ -104,16 +107,7 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); // - on power-on, and // - when the Debug Module requests an NDM reset (for non-DebugModule). -`ifdef INCLUDE_GDB_CONTROL - let clk <- exposeCurrentClock; - Bool initial_reset_val = False; - Integer ndm_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for NDM - let ndm_reset_controller <- mkReset(ndm_reset_duration, initial_reset_val, clk); - - let ndm_reset <- mkResetEither (power_on_reset, ndm_reset_controller.new_rst); -`else let ndm_reset = power_on_reset; -`endif // ================================================================ // STATE @@ -140,7 +134,6 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); Bool v2 <- $test$plusargs ("v2"); Bit #(4) verbosity = ((v2 ? 2 : (v1 ? 1 : 0))); Bit #(64) logdelay = 0; // # of instructions after which to set verbosity - soc_top.set_verbosity (verbosity, logdelay); // ---------------- // Load optional tohost and fromhost addrs from symbol-table file @@ -165,36 +158,6 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); endfunction // ================================================================ - -`ifdef INCLUDE_GDB_CONTROL - // ================================================================ - // NDM reset from DM - - Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0); - - rule rl_ndm_reset (rg_ndm_reset_delay == 0); - let x <- soc_top.ndm_reset_client.request.get; - ndm_reset_controller.assertReset; - rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 200); // NOTE: heuristic - - $display ("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - cur_cycle, ndm_reset_duration); - endrule - - rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0); - if (rg_ndm_reset_delay == 1) begin - fa_reset_actions; - Bool is_running = True; - soc_top.ndm_reset_client.response.put (is_running); - $display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - cur_cycle); - end - rg_ndm_reset_delay <= rg_ndm_reset_delay - 1; - endrule - // ================================================================ -`endif - - // ================================================================ // BEHAVIOR Reg #(Bool) rg_banner_printed <- mkReg (False); @@ -376,7 +339,8 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); rule rl_handle_external_req_read_request (req.op == external_control_req_op_read_control_fabric); f_external_control_reqs.deq; - soc_top.dmi.read_addr (truncate (req.arg1)); + soc_top.debug_subordinate.ar.put(AXI4Lite_ARFlit { araddr: truncate (req.arg1) + , arprot: ?, aruser: ? }); if (dmi_verbosity != 0) begin $display ("%0d: %m.rl_handle_external_req_read_request", cur_cycle); $display (" ", fshow (req)); @@ -384,8 +348,8 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); endrule rule rl_handle_external_req_read_response; - let x <- soc_top.dmi.read_data; - let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: signExtend (x)}; + let x <- get (soc_top.debug_subordinate.r); + let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: signExtend (x.rdata)}; f_external_control_rsps.enq (rsp); if (dmi_verbosity != 0) begin $display ("%0d: %m.rl_handle_external_req_read_response", cur_cycle); @@ -395,7 +359,10 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); rule rl_handle_external_req_write (req.op == external_control_req_op_write_control_fabric); f_external_control_reqs.deq; - soc_top.dmi.write (truncate (req.arg1), truncate (req.arg2)); + soc_top.debug_subordinate.aw.put(AXI4Lite_AWFlit { awaddr: truncate (req.arg1) + , awprot: ?, awuser: ? }); + soc_top.debug_subordinate.w.put(AXI4Lite_WFlit { wdata: truncate (req.arg2) + , wstrb: ~0, wuser: ? }); // let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: 0}; // f_external_control_rsps.enq (rsp); if (dmi_verbosity != 0) begin @@ -404,6 +371,8 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); end endrule + rule rl_drain_debug_write_rsps; soc_top.debug_subordinate.b.drop; endrule + rule rl_handle_external_req_err ( (req.op != external_control_req_op_read_control_fabric) && (req.op != external_control_req_op_write_control_fabric)); f_external_control_reqs.deq;