From 7608543da5ba8e6ad479662a968f314d5aa8be5e Mon Sep 17 00:00:00 2001
From: Jonathan Woodruff <jdw57@cam.ac.uk>
Date: Thu, 1 Feb 2024 10:07:48 +0000
Subject: [PATCH] Move back to more traditional implementation of the forwarded
 BRAM, which also workst.

---
 .../RISCY_OOO/coherence/src/RWBramCore.bsv    | 46 ++++++++++++++-----
 1 file changed, 35 insertions(+), 11 deletions(-)

diff --git a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
index 5250314..8ce2239 100644
--- a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
@@ -36,7 +36,6 @@
 
 import BRAMCore::*;
 import Fifos::*;
-import RegFile::*;
 
 interface RWBramCore#(type addrT, type dataT);
     method Action wrReq(addrT a, dataT d);
@@ -78,18 +77,43 @@ module mkRWBramCore(RWBramCore#(addrT, dataT)) provisos(
 endmodule
 
 module mkRWBramCoreForwarded(RWBramCore#(addrT, dataT)) provisos(
-        Bits#(addrT, addr_sz),
-        Bounded#(addrT),
-        Bits#(dataT, data_sz));
+    Bits#(addrT, addrSz), Bits#(dataT, dataSz), Eq#(addrT)
+);
+    BRAM_DUAL_PORT#(addrT, dataT) bram <- mkBRAMCore2(valueOf(TExp#(addrSz)), False);
+    BRAM_PORT#(addrT, dataT) wrPort = bram.a;
+    BRAM_PORT#(addrT, dataT) rdPort = bram.b;
+    // 1 elem pipeline fifo to add guard for read req/resp
+    // must be 1 elem to make sure rdResp is not corrupted
+    // BRAMCore should not change output if no req is made
+    Fifo#(1, void) rdReqQ <- mkPipelineFifo;
+    Reg#(addrT) readAddr[2] <- mkCReg(2,?);
+    Reg#(addrT) currentWriteAddr <- mkRegU;
+    Reg#(dataT) currentWriteData <- mkRegU;
 
-	  RegFile#(addrT,dataT) regFile <- mkRegFileWCF(minBound, maxBound); // BRAM
-	  Fifo#(1, addrT) readReq <- mkPipelineFifo;
+    rule doRead;
+        rdPort.put(False, readAddr[1], ?);
+    endrule
 
-  	method Action rdReq(addrT a) = readReq.enq(a);
-    method dataT rdResp() = regFile.sub(readReq.first());
-    method rdRespValid = readReq.notEmpty;
-    method Action deqRdResp = readReq.deq();
-    method Action wrReq(addrT a, dataT x) = regFile.upd(a,x);
+    method Action wrReq(addrT a, dataT d);
+        wrPort.put(True, a, d);
+        currentWriteAddr <= a; //Forward data, if read happens on same cycle
+        currentWriteData <= d;
+    endmethod
+
+    method Action rdReq(addrT a);
+        readAddr[0] <= a;
+        rdReqQ.enq(?);
+    endmethod
+
+    method dataT rdResp if(rdReqQ.notEmpty);
+        return (readAddr[0] == currentWriteAddr) ? currentWriteData : rdPort.read;
+    endmethod
+
+    method rdRespValid = rdReqQ.notEmpty;
+
+    method Action deqRdResp;
+        rdReqQ.deq;
+    endmethod
 endmodule
 
 module mkRWBramCoreUG(RWBramCore#(addrT, dataT)) provisos(