diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
index 9b0d9c1..510174d 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
@@ -239,11 +239,15 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
                            || isValid (x.regs.src3)
                            || fn_ArchReg_is_FpuReg (x.regs.dst));
         let mstatus   = csrf.rd (CSRmstatus);
-        Bool fs_trap = ((mstatus [14:13] == 2'b00) && fpr_access);
 
         // Check CSR access permission
         Bool csr_access_trap = False;
         if (x.dInst.iType == Csr) begin
+           if (x.dInst.csr matches tagged Valid .c) begin
+              case (c)
+                 CSRfcsr: fpr_access = True;
+              endcase
+           end
            Bit #(12) csr_addr  = case (x.dInst.csr) matches
                                     tagged Valid .c: pack (c);
                                     default:         12'hCFF;
@@ -264,6 +268,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
            csr_access_trap = (write_deny || priv_deny || unimplemented);
         end
 
+        Bool fs_trap = ((mstatus [14:13] == 2'b00) && fpr_access);
+
         // Check WFI trap (using a time-out of 0)
         Bit #(32) inst_WFI = 32'h_1050_0073;
         Bit #(1) mstatus_tw = mstatus [21];