From 76c0071c9e0acceecc7653d2d46b182b3dfe880c Mon Sep 17 00:00:00 2001
From: Karlis Susters <ks980@cam.ac.uk>
Date: Fri, 3 Mar 2023 14:23:13 +0000
Subject: [PATCH] Config for L1LL D Block-1 prefetcher

---
 builds/Resources/Include_RISCY_Config.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk
index ee59540..2ad8b1f 100644
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -45,9 +45,9 @@ SIM_LLC_ARBITER_LAT ?=
 # default check cache deadlock and rename error
 CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
-INSTR_PREFETCHER_LOCATION ?= L1LL
+INSTR_PREFETCHER_LOCATION ?= NONE
 INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW
-DATA_PREFETCHER_LOCATION ?= NONE
+DATA_PREFETCHER_LOCATION ?= L1LL
 DATA_PREFETCHER_TYPE ?= BLOCK
 
 # clk frequency depends on core size