Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Added counting code for return instructions

Browse Source
This commit is contained in:
Franz Fuchs
2021-06-22 18:01:32 +01:00
parent 8f45238b5d
commit 76cdc13a50
3 changed files with 43 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
View File

@@ -198,6 +198,8 @@ interface AluExeInput;
// check previous branch targets
method Bool checkTarget(CapMem ppc);
// check (previous) return targets
method Bool checkReturnTarget(CapMem ppc);
endinterface
interface AluExePipeline;
@@ -294,6 +296,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
let ppc = inIfc.rob_getPredPC(x.tag);
let orig_inst = inIfc.rob_getOrig_Inst (x.tag);
// TODO: split into Br, jumps, and rets
`ifdef PERFORMANCE_MONITORING
if(x.dInst.iType == Br || x.dInst.iType == Jr || x.dInst.iType == CJALR) begin
$display("BRANCH pc = ", fshow(pc), ", ppc = ", fshow(ppc));

21
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -134,6 +134,8 @@ interface CommitInput;
// update branch targets
method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets);
// update return targets
method Action updateReturnTargets(Vector#(SupSize, Maybe#(CapMem)) returnTargets);
`ifdef INCLUDE_TANDEM_VERIF
interface Vector #(SupSize, Put #(Trace_Data2)) v_to_TV;
@@ -1093,9 +1095,12 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
// update targets vector
Vector#(SupSize, Maybe#(CapMem)) targets;
// update return targets vector
Vector#(SupSize, Maybe#(CapMem)) returnTargets;
// compute what actions to take
for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
Maybe#(CapMem) tar = tagged Invalid;
Maybe#(CapMem) retTar = tagged Invalid;
if(!stop && rob.deqPort[i].canDeq) begin
let x = rob.deqPort[i].deq_data;
let inst_tag = rob.deqPort[i].getDeqInstTag;
@@ -1139,6 +1144,20 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
// inst can be committed, deq it
rob.deqPort[i].deq;
// return address stack link reg is x1 or x5
function Bool linkedR(Maybe#(ArchRIndx) register);
Bool res = False;
if (register matches tagged Valid .r &&& (r == tagged Gpr 1 || r == tagged Gpr 5)) begin
res = True;
end
return res;
endfunction
// update return target
if((x.iType == J || x.iType == CJAL) && linkedR(x.dst)) begin
retTar = tagged Valid x.ppc_vaddr_csrData.PPC;
end
// update target
if(x.iType == CJALR || x.iType == Jr) begin
tar = tagged Valid x.ppc_vaddr_csrData.PPC;
@@ -1220,6 +1239,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
end
targets[i] = tar;
returnTargets[i] = retTar;
end
rg_serial_num <= rg_serial_num + instret;
@@ -1285,6 +1305,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
`endif
inIfc.updateTargets(targets);
inIfc.updateReturnTargets(returnTargets);
`ifdef RVFI
rvfiQ.enq(rvfis);