diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index dbdc87e..23b35b3 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -318,8 +318,8 @@ module mkFetchStage(FetchStage);
     // rule ordering: Fetch1 (BTB+TLB) < Fetch3 (decode & dir pred) < redirect method
     // Fetch1 < Fetch3 to avoid bypassing path on PC and epochs
 
-    Bool verbose = True;
-    Integer verbosity = 1;
+    Bool verbose = False;
+    Integer verbosity = 0;
 
     // Basic State Elements
     Reg#(Bool) started <- mkReg(False);
@@ -430,12 +430,6 @@ module mkFetchStage(FetchStage);
         //dii_instIds.enq(reqs);
         //dii_id_next <= next_id + `sizeSup;
     //endrule
-    
-    Reg#(Bit#(4)) ticker <- mkReg(0);
-    rule tick;
-        ticker <= ticker + 1;
-        if (ticker == 0) $display("%t : tick", $time);
-    endrule
 `endif
 
    // Predict the next fetch-PC based only on current PC (without
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index 3ef8faf..abce968 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -188,7 +188,7 @@ interface MemExePipeline;
 endinterface
 
 module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
-    Bool verbose = True;
+    Bool verbose = False;
 
     // we change cache request in case of single core, becaues our MSI protocol
     // is not good with single core
diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
index 66217cd..b43fc4f 100644
--- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
@@ -251,7 +251,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
                     ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= PPC (cf.nextPc);
                 end
 `ifdef RVFI
-                $display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
+                //$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
                 traceBundle[pvc_finishAlu_port(i)] <= tb;
 `endif
                 doAssert(isValid(csr) == isValid(csrData), "csr valid should match");
@@ -294,7 +294,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
         // update VAddr
         ppc_vaddr_csrData[pvc_finishMem_port] <= VAddr (vaddr);
 `ifdef RVFI
-        $display("%t : traceBundle = ", $time(), fshow(tb), " in setExecuted_doFinishMem for %x", pc);
+        //$display("%t : traceBundle = ", $time(), fshow(tb), " in setExecuted_doFinishMem for %x", pc);
         traceBundle[pvc_finishMem_port] <= tb;
 `endif
         // update access at commit
@@ -340,7 +340,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
         diid <= x.diid;
 `endif
 `ifdef RVFI
-        $display("%t : traceBundle = ", $time(), fshow(x.traceBundle), " in write_enq for %x", pc);
+        //$display("%t : traceBundle = ", $time(), fshow(x.traceBundle), " in write_enq for %x", pc);
         traceBundle[pvc_enq_port] <= x.traceBundle;
 `endif
         // check
@@ -402,7 +402,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
         rob_inst_state[state_deqLSQ_port] <= Executed;
 `ifdef RVFI
         traceBundleMem <= tb;
-        $display("%t: Wrote tb for deqLSQ ", $time(), fshow(tb));
+        //$display("%t: Wrote tb for deqLSQ ", $time(), fshow(tb));
 `endif
         // record trap
         doAssert(!isValid(trap[trap_deqLSQ_port]), "cannot have trap");
diff --git a/src_Verifier/Toooba_RVFI_DII_Bridge.bsv b/src_Verifier/Toooba_RVFI_DII_Bridge.bsv
index b6c56fd..1591a91 100644
--- a/src_Verifier/Toooba_RVFI_DII_Bridge.bsv
+++ b/src_Verifier/Toooba_RVFI_DII_Bridge.bsv
@@ -69,7 +69,7 @@ module mkTooobaRVFIDIIBridge(Toooba_RVFI_DII_Bridge_IFC);
     FIFO#(Dii_Ids) seq_req <- mkFIFO;
     Reg#(Dii_Id) last_id <- mkReg(0);
     
-    Bool verbose = True;
+    Bool verbose = False;
     
     function Bool validReport(RVFI_DII_Execution#(DataSz,DataSz) trace);
         return (trace.rvfi_insn != dii_nop);