From b830f4bf414366e3dad24df6953fc55e762a9b22 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 19 Mar 2020 19:21:59 +0000 Subject: [PATCH] Resolve some issues to build on mac. This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv. Also this includes an update of the verilator flags that are needed for modern verilator. Finally, some verilator flag changes for building with LLVM. --- builds/Resources/Include_verilator.mk | 2 +- .../Verilator_resources/verilator_config.vlt | 12 ++++++------ src_Core/CPU/Core.bsv | 2 +- src_Core/CPU/CsrFile.bsv | 2 +- src_Core/CPU/MMIOPlatform.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/CCPipe.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/CrossBar.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/IBank.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/L1Bank.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/LLBank.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv | 2 +- src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv | 2 +- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 2 +- .../RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv | 2 +- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/DTlb.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/{Fifo.bsv => Fifos.bsv} | 0 src_Core/RISCY_OOO/procs/lib/ITlb.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv | 2 +- .../RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/LLCache.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/MemLoader.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/MulDiv.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv | 2 +- 38 files changed, 42 insertions(+), 42 deletions(-) rename src_Core/RISCY_OOO/procs/lib/{Fifo.bsv => Fifos.bsv} (100%) diff --git a/builds/Resources/Include_verilator.mk b/builds/Resources/Include_verilator.mk index da2b943..965efef 100644 --- a/builds/Resources/Include_verilator.mk +++ b/builds/Resources/Include_verilator.mk @@ -34,7 +34,7 @@ SIM_EXE_FILE = exe_HW_sim # --x-initial fast Optimize uninitialized value # --noassert Disable all assertions -VERILATOR_FLAGS = --stats -LDFLAGS -static --x-assign fast --x-initial fast --noassert +VERILATOR_FLAGS = --stats --x-assign fast --x-initial fast --noassert # VERILATOR_FLAGS = --stats -O3 -CFLAGS -O3 -LDFLAGS -static --x-assign fast --x-initial fast --noassert # Verilator flags: use the following to include code to generate VCDs diff --git a/builds/Resources/Verilator_resources/verilator_config.vlt b/builds/Resources/Verilator_resources/verilator_config.vlt index c0e8c0e..571b3a7 100644 --- a/builds/Resources/Verilator_resources/verilator_config.vlt +++ b/builds/Resources/Verilator_resources/verilator_config.vlt @@ -3,10 +3,10 @@ // Flags for verilator `verilator_config -lint_off -msg WIDTH -lint_off -msg CASEINCOMPLETE -lint_off -msg STMTDLY -lint_off -msg INITIALDLY -lint_off -msg UNSIGNED -lint_off -msg CMPCONST +lint_off -rule WIDTH +lint_off -rule CASEINCOMPLETE +lint_off -rule STMTDLY +lint_off -rule INITIALDLY +lint_off -rule UNSIGNED +lint_off -rule CMPCONST `verilog diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 0bb4aac..f49500c 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -33,7 +33,7 @@ import Assert::*; import Cntrs::*; import ConfigReg::*; import FIFO::*; -import Fifo::*; +import Fifos::*; import Ehr::*; import Connectable::*; diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index fbc6ad0..53af5cc 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -29,7 +29,7 @@ import DefaultValue::*; import ConcatReg::*; import ConfigReg::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import Vector::*; import FIFO::*; import GetPut::*; diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv index 83cbe1b..8273326 100644 --- a/src_Core/CPU/MMIOPlatform.bsv +++ b/src_Core/CPU/MMIOPlatform.bsv @@ -46,7 +46,7 @@ import GetPut_Aux :: *; // ---------------- // From MIT RISCY-OOO -import Fifo::*; +import Fifos::*; import Types::*; import ProcTypes::*; import CCTypes::*; diff --git a/src_Core/RISCY_OOO/coherence/src/CCPipe.bsv b/src_Core/RISCY_OOO/coherence/src/CCPipe.bsv index bb9dede..53f9a4d 100644 --- a/src_Core/RISCY_OOO/coherence/src/CCPipe.bsv +++ b/src_Core/RISCY_OOO/coherence/src/CCPipe.bsv @@ -22,7 +22,7 @@ // SOFTWARE. import Ehr::*; -import Fifo::*; +import Fifos::*; import Vector::*; import RWBramCore::*; import FShow::*; diff --git a/src_Core/RISCY_OOO/coherence/src/CrossBar.bsv b/src_Core/RISCY_OOO/coherence/src/CrossBar.bsv index f3d31a5..44619fd 100644 --- a/src_Core/RISCY_OOO/coherence/src/CrossBar.bsv +++ b/src_Core/RISCY_OOO/coherence/src/CrossBar.bsv @@ -28,7 +28,7 @@ import CacheUtils::*; import CCTypes::*; import Types::*; import FShow::*; -import Fifo::*; +import Fifos::*; import Ehr::*; typedef struct { diff --git a/src_Core/RISCY_OOO/coherence/src/IBank.bsv b/src_Core/RISCY_OOO/coherence/src/IBank.bsv index d00305a..e4cea2f 100644 --- a/src_Core/RISCY_OOO/coherence/src/IBank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/IBank.bsv @@ -40,7 +40,7 @@ import CCPipe::*; import L1Pipe ::*; import FShow::*; import DefaultValue::*; -import Fifo::*; +import Fifos::*; import CacheUtils::*; import Performance::*; import LatencyTimer::*; diff --git a/src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv b/src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv index e9f54d7..d5ad3b3 100644 --- a/src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv +++ b/src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv @@ -31,7 +31,7 @@ import Types::*; import CCTypes::*; import DefaultValue::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import MshrDeadlockChecker::*; // MSHR dependency chain invariant: diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv index 3aaa220..4c0e41e 100644 --- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv @@ -41,7 +41,7 @@ import L1Pipe ::*; import FShow::*; import DefaultValue::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import CacheUtils::*; import CrossBar::*; import Performance::*; diff --git a/src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv b/src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv index 2a6c2e3..b603408 100644 --- a/src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv +++ b/src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv @@ -30,7 +30,7 @@ import Types::*; import CCTypes::*; import DefaultValue::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import MshrDeadlockChecker::*; // MSHR dependency chain invariant: diff --git a/src_Core/RISCY_OOO/coherence/src/LLBank.bsv b/src_Core/RISCY_OOO/coherence/src/LLBank.bsv index 944d744..b5bf19d 100644 --- a/src_Core/RISCY_OOO/coherence/src/LLBank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/LLBank.bsv @@ -31,7 +31,7 @@ import CCPipe::*; import LLPipe ::*; import FShow::*; import DefaultValue::*; -import Fifo::*; +import Fifos::*; import CacheUtils::*; import Performance::*; import LatencyTimer::*; diff --git a/src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv b/src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv index 6a903ba..b910840 100644 --- a/src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv +++ b/src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv @@ -30,7 +30,7 @@ import Types::*; import CCTypes::*; import DefaultValue::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import MshrDeadlockChecker::*; // MSHR dependency chain invariant: diff --git a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv index 8af253f..e0233a8 100644 --- a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv +++ b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv @@ -22,7 +22,7 @@ // SOFTWARE. import BRAMCore::*; -import Fifo::*; +import Fifos::*; interface RWBramCore#(type addrT, type dataT); method Action wrReq(addrT a, dataT d); diff --git a/src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv b/src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv index ca1fe14..313cec6 100644 --- a/src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv +++ b/src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv @@ -22,7 +22,7 @@ // SOFTWARE. import Vector::*; -import Fifo::*; +import Fifos::*; import CCTypes::*; import RWBramCore::*; diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv index 145cf61..8dd9d47 100644 --- a/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv @@ -39,7 +39,7 @@ import CCPipe::*; import SelfInvIPipe ::*; import FShow::*; import DefaultValue::*; -import Fifo::*; +import Fifos::*; import CacheUtils::*; import Performance::*; import LatencyTimer::*; diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv index 0b35b04..19f6b14 100644 --- a/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv +++ b/src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv @@ -26,7 +26,7 @@ import ConfigReg::*; import Vector::*; import FShow::*; import Types::*; -import Fifo::*; +import Fifos::*; import CCTypes::*; import CCPipe::*; import RWBramCore::*; diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv index 95de324..cada0f1 100644 --- a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv @@ -41,7 +41,7 @@ import SelfInvL1Pipe ::*; import FShow::*; import DefaultValue::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import CacheUtils::*; import CrossBar::*; import Performance::*; diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv index 43d0502..b3716a4 100644 --- a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv +++ b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv @@ -25,7 +25,7 @@ import Assert::*; import ConfigReg::*; import Vector::*; import FShow::*; -import Fifo::*; +import Fifos::*; import Types::*; import CCTypes::*; import CCPipe::*; diff --git a/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv b/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv index 0c0329f..089b2c0 100644 --- a/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv @@ -30,7 +30,7 @@ import LLCRqMshr::*; import CCPipe::*; import SelfInvLLPipe ::*; import FShow::*; -import Fifo::*; +import Fifos::*; import CacheUtils::*; import Performance::*; import LatencyTimer::*; diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index b0c85dc..f848372 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -31,7 +31,7 @@ import ClientServer::*; import Connectable::*; import Decode::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import GetPut::*; import MemoryTypes::*; import Types::*; diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index a8a077b..7cb7b4c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -27,7 +27,7 @@ import BuildVector::*; import GetPut::*; import ClientServer::*; import Cntrs::*; -import Fifo::*; +import Fifos::*; import Types::*; import ProcTypes::*; import MemoryTypes::*; diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index c15b93b..a95c2c2 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -26,7 +26,7 @@ import Vector::*; import GetPut::*; import Cntrs::*; -import Fifo::*; +import Fifos::*; import FIFO::*; import Types::*; import ProcTypes::*; diff --git a/src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv b/src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv index 7570601..a443bb3 100644 --- a/src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv +++ b/src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv @@ -29,7 +29,7 @@ import GetPut::*; import ClientServer::*; import Connectable::*; import Vector::*; -import Fifo::*; +import Fifos::*; import Ehr::*; import FIFO::*; import FIFOF::*; diff --git a/src_Core/RISCY_OOO/procs/lib/DTlb.bsv b/src_Core/RISCY_OOO/procs/lib/DTlb.bsv index 504aa7d..d06ce3f 100644 --- a/src_Core/RISCY_OOO/procs/lib/DTlb.bsv +++ b/src_Core/RISCY_OOO/procs/lib/DTlb.bsv @@ -31,7 +31,7 @@ import TlbTypes::*; import Performance::*; import FullAssocTlb::*; import ConfigReg::*; -import Fifo::*; +import Fifos::*; import Cntrs::*; import SafeCounter::*; import CacheUtils::*; diff --git a/src_Core/RISCY_OOO/procs/lib/Fifo.bsv b/src_Core/RISCY_OOO/procs/lib/Fifos.bsv similarity index 100% rename from src_Core/RISCY_OOO/procs/lib/Fifo.bsv rename to src_Core/RISCY_OOO/procs/lib/Fifos.bsv diff --git a/src_Core/RISCY_OOO/procs/lib/ITlb.bsv b/src_Core/RISCY_OOO/procs/lib/ITlb.bsv index 7851d68..dcb435b 100644 --- a/src_Core/RISCY_OOO/procs/lib/ITlb.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ITlb.bsv @@ -31,7 +31,7 @@ import TlbTypes::*; import Performance::*; import FullAssocTlb::*; import ConfigReg::*; -import Fifo::*; +import Fifos::*; import Cntrs::*; import SafeCounter::*; import CacheUtils::*; diff --git a/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv b/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv index cd97b39..85f3294 100644 --- a/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv +++ b/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv @@ -33,7 +33,7 @@ import CacheUtils::*; import Types::*; import ProcTypes::*; import Performance::*; -import Fifo::*; +import Fifos::*; import CCTypes::*; import L1Pipe::*; import L1CRqMshr::*; diff --git a/src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv b/src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv index 8e60b28..0402726 100644 --- a/src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv +++ b/src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv @@ -33,7 +33,7 @@ import Performance::*; import FullAssocTlb::*; import ConfigReg::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import Cntrs::*; import SafeCounter::*; import CacheUtils::*; diff --git a/src_Core/RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv b/src_Core/RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv index 0aa20eb..ed81eed 100644 --- a/src_Core/RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv +++ b/src_Core/RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv @@ -30,7 +30,7 @@ import Types::*; import CCTypes::*; import DefaultValue::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import MshrDeadlockChecker::*; import LLCRqMshr::*; diff --git a/src_Core/RISCY_OOO/procs/lib/LLCache.bsv b/src_Core/RISCY_OOO/procs/lib/LLCache.bsv index d718569..38badac 100644 --- a/src_Core/RISCY_OOO/procs/lib/LLCache.bsv +++ b/src_Core/RISCY_OOO/procs/lib/LLCache.bsv @@ -29,7 +29,7 @@ import Connectable::*; import GetPut::*; import Assert::*; import CacheUtils::*; -import Fifo::*; +import Fifos::*; import Types::*; import ProcTypes::*; import CCTypes::*; diff --git a/src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv b/src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv index 4432739..7f89a8d 100644 --- a/src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv @@ -26,7 +26,7 @@ import ConfigReg::*; import ProcTypes::*; import MMIOAddrs::*; import CacheUtils::*; -import Fifo::*; +import Fifos::*; import Amo::*; import MMIOInst::*; diff --git a/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv b/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv index c4b4884..523fc7f 100644 --- a/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv @@ -23,7 +23,7 @@ import Vector::*; import ConfigReg::*; -import Fifo::*; +import Fifos::*; import Types::*; import ProcTypes::*; import CCTypes::*; diff --git a/src_Core/RISCY_OOO/procs/lib/MemLoader.bsv b/src_Core/RISCY_OOO/procs/lib/MemLoader.bsv index 0604c28..06ac097 100644 --- a/src_Core/RISCY_OOO/procs/lib/MemLoader.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MemLoader.bsv @@ -29,7 +29,7 @@ import Connectable::*; import FShow::*; import FIFO::*; import Vector::*; -import Fifo::*; +import Fifos::*; import Types::*; import ProcTypes::*; import CCTypes::*; diff --git a/src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv b/src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv index dee05bc..7b8636d 100644 --- a/src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv @@ -21,7 +21,7 @@ // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE // SOFTWARE. -import Fifo::*; +import Fifos::*; typedef union tagged { reqT Req; diff --git a/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv b/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv index e05326a..20a2429 100644 --- a/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv @@ -25,7 +25,7 @@ import BuildVector::*; import Types::*; import ProcTypes::*; -import Fifo::*; +import Fifos::*; import FIFO::*; import XilinxIntMul::*; import XilinxIntDiv::*; diff --git a/src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv b/src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv index f1c6c3b..6abce64 100644 --- a/src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv @@ -24,7 +24,7 @@ `include "ProcConfig.bsv" import Vector::*; -import Fifo::*; +import Fifos::*; import ProcTypes::*; import CsrFile::*; // for mkReadOnlyReg import Ehr::*; diff --git a/src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv b/src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv index aae4f1a..aa87f8f 100644 --- a/src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv +++ b/src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv @@ -24,7 +24,7 @@ import Vector::*; import Assert::*; import Ehr::*; -import Fifo::*; +import Fifos::*; import Types::*; import ProcTypes::*; import TlbTypes::*;